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27 条记录 (耗时 0.016 秒)

    Integrated circuit device
    2.
    发明授权
    Integrated circuit device 有权
    具有用于形成线圈的多个导体图案的集成电路装置

    公开(公告)号：US08633577B2

    公开(公告)日：2014-01-21

    申请号：US12162059

    申请日：2007-01-16

    申请人： Yoshihiro Nakagawa ,  Muneo Fukaishi

    发明人： Yoshihiro Nakagawa ,  Muneo Fukaishi

    IPC分类号： H01L23/52

    CPC分类号： H01L23/5227 ,  H01F17/0006 ,  H01F21/12 ,  H01F38/14 ,  H01F2017/0073 ,  H01F2021/125 ,  H01F2038/143 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Provided on a chip are a plurality of conductor patterns for forming a coil, and a connection-relationship control device for controlling connection between adjacent conductor patterns. By switching the connection relationship of the conductor patterns by the connection-relationship control device, it is possible to form a coil of a desired shape at a desired position.

    摘要翻译： 设置在芯片上的是用于形成线圈的多个导体图案和用于控制相邻导体图案之间的连接的连接关系控制装置。 通过由连接关系控制装置切换导体图形的连接关系，可以在期望的位置形成期望形状的线圈。

    Signal transmission system and semiconductor integrated circuit device
    3.
    发明授权
    Signal transmission system and semiconductor integrated circuit device 有权
    信号传输系统和半导体集成电路器件

    公开(公告)号：US08477855B2

    公开(公告)日：2013-07-02

    申请号：US12162687

    申请日：2007-01-17

    申请人： Muneo Fukaishi ,  Yoshihiro Nakagawa ,  Tadahiro Kuroda

    发明人： Muneo Fukaishi ,  Yoshihiro Nakagawa ,  Tadahiro Kuroda

    IPC分类号： H04L7/02 ,  H04B5/00

    CPC分类号： H04B5/02 ,  H01L23/48 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Disclosed is a semiconductor integrated circuit device including a transmitting circuit and a receiving coil inductively coupled to a transmitting coil. The transmitting circuit transmits data by supplying a current through the transmitting coil not at the time of transition of data but at every rising edge or falling edge of a clock used in transmission of data. At every rising edge or falling edge of the clock, a receiving circuit captures a voltage induced in the receiving coil due to the current flowing through the transmitting coil, reproduces the transmitted data and outputs the reproduced data.

    摘要翻译： 公开了一种半导体集成电路器件，其包括感应耦合到发送线圈的发送电路和接收线圈。 发送电路不是在数据转换时通过发送线圈提供电流而是在数据传输中使用的时钟的每个上升沿或下降沿发送数据。 在时钟的每个上升沿或下降沿，接收电路捕获由于流过发送线圈的电流而在接收线圈中感应的电压，再现发送的数据并输出再现的数据。

    SIGNAL TRANSMISSION SYSTEM AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
    4.
    发明申请
    SIGNAL TRANSMISSION SYSTEM AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 有权
    信号传输系统和半导体集成电路设备

    公开(公告)号：US20090196388A1

    公开(公告)日：2009-08-06

    申请号：US12162687

    申请日：2007-01-17

    申请人： Muneo Fukaishi ,  Yoshihiro Nakagawa ,  Tadahiro Kuroda

    发明人： Muneo Fukaishi ,  Yoshihiro Nakagawa ,  Tadahiro Kuroda

    IPC分类号： H04L7/02 ,  H04B5/00

    CPC分类号： H04B5/02 ,  H01L23/48 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Disclosed is a semiconductor integrated circuit device including a transmitting circuit and a receiving coil inductively coupled to a transmitting coil. The transmitting circuit transmits data by supplying a current through the transmitting coil not at the time of transition of data but at every rising edge or falling edge of a clock used in transmission of data. At every rising edge or falling edge of the clock, a receiving circuit captures a voltage induced in the receiving coil due to the current flowing through the transmitting coil, reproduces the transmitted data and outputs the reproduced data.

    摘要翻译： 公开了一种半导体集成电路器件，其包括感应耦合到发送线圈的发送电路和接收线圈。 发送电路不是在数据转换时通过发送线圈提供电流而是在数据传输中使用的时钟的每个上升沿或下降沿发送数据。 在时钟的每个上升沿或下降沿，接收电路捕获由于流过发送线圈的电流而在接收线圈中感应的电压，再现发送的数据并输出再现的数据。

    INTEGRATED CIRCUIT DEVICE
    5.
    发明申请
    INTEGRATED CIRCUIT DEVICE 有权
    集成电路设备

    公开(公告)号：US20090014892A1

    公开(公告)日：2009-01-15

    申请号：US12162059

    申请日：2007-01-16

    申请人： Yoshihiro Nakagawa ,  Muneo Fukaishi

    发明人： Yoshihiro Nakagawa ,  Muneo Fukaishi

    IPC分类号： H01L23/52

    CPC分类号： H01L23/5227 ,  H01F17/0006 ,  H01F21/12 ,  H01F38/14 ,  H01F2017/0073 ,  H01F2021/125 ,  H01F2038/143 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Provided on a chip are a plurality of conductor patterns for forming a coil, and a connection-relationship control device for controlling connection between adjacent conductor patterns. By switching the connection relationship of the conductor patterns by the connection-relationship control device, it is possible to form a coil of a desired shape at a desired position.

    摘要翻译： 设置在芯片上的是用于形成线圈的多个导体图案和用于控制相邻导体图案之间的连接的连接关系控制装置。 通过由连接关系控制装置切换导体图形的连接关系，可以在期望的位置形成期望形状的线圈。

    Stacked semiconductor memory device
    8.
    发明申请
    Stacked semiconductor memory device 有权
    堆叠半导体存储器件

    公开(公告)号：US20050286334A1

    公开(公告)日：2005-12-29

    申请号：US11151213

    申请日：2005-06-14

    申请人： Hideaki Saito ,  Yasuhiko Hagihara ,  Muneo Fukaishi ,  Masayuki Mizuno ,  Hiroaki Ikeda ,  Kayoko Shibata

    发明人： Hideaki Saito ,  Yasuhiko Hagihara ,  Muneo Fukaishi ,  Masayuki Mizuno ,  Hiroaki Ikeda ,  Kayoko Shibata

    IPC分类号： G11C5/04 ,  G11C5/06 ,  G11C8/00 ,  H01L25/065

    CPC分类号： G11C5/04 ,  G11C5/063 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2225/06527 ,  H01L2225/06555 ,  H01L2924/01019 ,  H01L2924/10253 ,  H01L2924/00

    摘要： A three-dimensional semiconductor memory device having the object of decreasing the interconnection capacitance that necessitates electrical charge and discharge during data transfer and thus decreasing power consumption is provided with: a plurality of memory cell array chips, in which sub-banks that are the divisions of bank memory are organized and arranged to correspond to input/output bits, are stacked on a first semiconductor chip; and interchip interconnections for connecting the memory cell arrays such that corresponding input/output bits of the sub-banks are the same, these interchip interconnections being provided in a number corresponding to the number of input/output bits and passing through the memory cell array chips in the direction of stacking.

    摘要翻译： 具有减少在数据传送期间需要充电和放电并因此降低功耗的互连电容的目的的三维半导体存储器件具有：多个存储单元阵列芯片，其中作为分区的子行 组合存储器并且被布置为对应于输入/输出位，堆叠在第一半导体芯片上; 以及用于连接存储单元阵列的芯片间互连，使得子组的相应输入/输出位相同，这些芯片间互连以与输入/输出位数相对应的数量提供并通过存储单元阵列芯片 在堆叠的方向。

    Phase locked loop circuit
    9.
    发明授权
    Phase locked loop circuit 有权
    锁相环电路

    公开(公告)号：US06377127B1

    公开(公告)日：2002-04-23

    申请号：US09711407

    申请日：2000-11-13

    申请人： Muneo Fukaishi

    发明人： Muneo Fukaishi

    IPC分类号： H03L708

    CPC分类号： H03L7/0891

    摘要： In a phase locked loop circuit, a phase difference signal (an up signal and a down signal) is supplied from a phase comparator to a serial-to-parallel converting circuit, and an output of the serial-to-parallel converting circuit is supplied to an up-down counter having a count value is counted up or down in accordance with the phase difference detected by the phase comparator. A voltage controlled oscillator generates an oscillation signal having the frequency controlled in accordance with the count value of the up-down counter. Thus, since the phase difference signal is serial-to-parallel converted, the rate of the phase difference signal is lowered, so that the operation speed of the up-down counter can be relaxed. Therefore, the operation speed of the phase locked loop circuit can be elevated with elevating the operation speed of the up-down counter.

    摘要翻译： 在锁相环电路，相位差信号（上行信号和下行信号）从相位比较器提供给串行 - 并行转换电路，以及串行 - 并行转换电路的输出被供给 具有计数值的升降计数器根据由相位比较器检测的相位差向上或向下计数。 压控振荡器产生具有根据升降计数器的计数值进行频率控制的振荡信号。 因此，由于相位差信号是串行到并行转换，相位差信号的速率下降，从而使升降计数器的操作速度可以放宽。 因此，通过提高上下计数器的操作速度，能够提高锁相环电路的动作速度。

    Phase comparator operable at half frequency of input signal
    10.
    发明授权
    Phase comparator operable at half frequency of input signal 有权
    相位比较器在输入信号的一半频率下工作

    公开(公告)号：US06314151B1

    公开(公告)日：2001-11-06

    申请号：US09167733

    申请日：1998-10-07

    申请人： Muneo Fukaishi

    发明人： Muneo Fukaishi

    IPC分类号： H04D324

    CPC分类号： H03L7/0891 ,  H03D13/004 ,  H04L7/033

    摘要： In a phase comparator, a first data fetching circuit fetches an input signal in response to a transition timing of a clock signal having a frequency about half that of the input signal, and a second data fetching circuit fetches the output signal of the first data fetching circuit in response to a transition timing of an inverted signal of the clock signal. A first exclusive OR performs an exclusive OR operation upon the input signal and the output signal of the first data fetching circuit. and a second exclusive OR circuit performs an exclusive OR operation upon the output signals of the first and second data fetching circuits. An inverter inverts the output signal of the first exclusive OR circuit. A first AND circuit performs an AND operation upon the output signal of the second data fetching circuit and the output of the exclusive OR circuit, a second AND circuit performs an AND operation upon the output signal of the first exclusive OR circuit and the output of the first AND circuit to generate a leading signal, and a third AND circuit performs an AND operation upon the output signal of the inverter and the output of the,first AND circuit to generate a lagging signal.

    摘要翻译： 在相位比较器中，第一数据取出电路响应于具有大约为输入信号的一半的时钟信号的时钟信号的转换定时取入输入信号，第二数据取出电路取出第一数据取出的输出信号 响应于时钟信号的反相信号的转变定时。 第一异或执行对第一数据提取电路的输入信号和输出信号的异或运算。 并且第二异或电路对第一和第二数据提取电路的输出信号执行异或运算。 逆变器反相第一异或电路的输出信号。 第一AND电路对第二数据取出电路的输出信号和异或电路的输出执行AND运算，第二AND电路根据第一异或电路的输出信号和 第一AND电路产生前导信号，第三AND电路根据反相器的输出信号和第一AND电路的输出执行AND运算，以产生滞后信号。