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公开(公告)号：US5568479A
公开(公告)日：1996-10-22
申请号：US541395
申请日：1995-10-10
CPC分类号： H04L49/3009 , H04L49/253 , H04L49/255 , H04L49/3081 , H04Q11/0478 , H04L2012/561 , H04L2012/5615 , H04L2012/5616 , H04L2012/563 , H04L2012/5652 , H04L49/30 , H04L49/503
摘要： The present invention relates to a system for controlling a miscellaneous device such as a remote device associated with an exchange which handles a fixed length cell with a control field and an information field. The object of the invention is to offer a system where an exchange can control a miscellaneous device such as a remote device in accordance with the feature of the exchange. The exchange includes a call processor, a switch and a signal device. In order to control the miscellaneous device, a path is formed between the signal device and the miscellaneous device. Control information from the call processor is cellulated. The path notifies the miscellaneous device of the control information including cell via the switch to control the miscellaneous device by the exchange.
摘要翻译： 本发明涉及一种用于控制诸如与交换机相关联的诸如与具有控制字段和信息字段的固定长度单元相关联的其他设备的系统。 本发明的目的是提供一种系统，其中交换机可以根据交换机的特征来控制诸如远程设备的其他设备。 交换机包括呼叫处理器，交换机和信号设备。 为了控制杂项设备，在信号设备和其他设备之间形成路径。 来自呼叫处理器的控制信息被通话。 该路径通过交换机将包括小区的控制信息通知给杂项设备，以通过交换机来控制其他设备。
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公开(公告)号：US5488606A
公开(公告)日：1996-01-30
申请号：US216149
申请日：1994-03-21
CPC分类号： H04L49/153 , H04L49/552 , H04L69/40 , H04L2012/5627 , H04L49/1523 , H04L49/30
摘要： An ATM (asynchronous transfer mode) exchange has a buffer for system #0 and a buffer for system #1 providing P-MEM's for storing data including an A bit and for a VCI/VPI currently in use is set to "1'. Upon detecting a switchover between the systems, every B bit is reset to "0". When the exchange while changing from a master to a slave receives a cell having a slave indication and while changing from a slave to a master it receives a cell having a master indication, respective systems rewrite B bits for VCI/VPI's of respective cells to "1". In the meantime, each of the P-MEM's calculates exclusive "OR" operations between the A bit and the B bit for every VCI/VPI, and further obtains a disjunction among all the exclusive "OR" operations thus obtained. Then, when both P-MEM's obtain "0" for their respective disjunctions, cells are read out from one of the buffers in the system changing from a slave to a master. This enables the ATM exchange having a switch duplexed by mutually asynchronous active and backup systems to switchover the systems without causing a cell to be duplicated or lost.
摘要翻译： ATM（异步传输模式）交换机具有用于系统＃0的缓冲器和用于系统＃1的缓冲器，提供用于存储包括A位的数据的P-MEM，并且当前使用的VCI / VPI被设置为“1” 检测系统之间的切换，每个B位复位为“0”，当从主机切换到从机的交换机接收到具有从机指示的单元，并且在从从机更改为主机时，接收具有 主指示，相应的系统将各单元的VCI / VPI的B位重写为“1”，同时每个P-MEM针对每个VCI / VPI计算A位和B位之间的独占“或”运算， 并且在所得到的所有排他“OR”运算中进一步获得分离，然后，当两个P-MEM对于它们各自的分离获得“0”时，从系统中的缓冲器之一读出小区从从属设备 主机，这使得ATM交换机具有通过相互异步双工的交换机 主动和备份系统切换系统，而不会导致单元被重复或丢失。
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3.发明授权
公开(公告)号：US5675587A
公开(公告)日：1997-10-07
申请号：US758061
申请日：1996-11-27
申请人： Yuzo Okuyama , Satoshi Kakuma , Shiro Uriu , Kazuo Hajikano
发明人： Yuzo Okuyama , Satoshi Kakuma , Shiro Uriu , Kazuo Hajikano
CPC分类号： H04L12/5601 , H04L49/3081 , H04L49/309 , H04L49/555 , H04Q11/0478 , H04L2012/5628 , H04L2012/5636 , H04L2012/5647 , H04L2012/5652
摘要： A test cell generating section periodically generates a pass determining test cell at preset timing, multiplexes them with user cells from a user line interface, and transmits the result of multiplexing to an ATM exchange. When no user cell is supplied from the user line interface, the test cell generating section transmits only the pass determining test cell to the ATM exchange. A cell determining section determines whether a cell supplied from the ATM exchange is a user cell or test cell, identifies/determines the pass based on information of the test cell and outputs only the user cell to the user line side when the supplied cell is the test cell.
摘要翻译： 测试小区生成部分在预定的定时周期性地生成通过确定测试小区，并将其与用户线路接口的用户小区进行复用，并将多路复用结果发送到ATM交换机。 当用户线路接口没有提供用户小区时，测试小区生成部分仅将通过确定测试小区发送到ATM交换机。 小区确定部分确定从ATM交换机提供的小区是否是用户小区或测试小区，当所提供的小区为所述小区时，基于所述测试小区的信息来识别/确定所述通过，并且仅将所述用户小区仅输出到所述用户线路侧 测试单元。
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公开(公告)号：US5654967A
公开(公告)日：1997-08-05
申请号：US565035
申请日：1995-11-30
申请人： Yuzo Okuyama , Satoshi Kakuma
发明人： Yuzo Okuyama , Satoshi Kakuma
CPC分类号： H04Q11/06
摘要： A delay-in-frames correction system in a switch unit in a PCM transmission line is used for data communication. A channel data storage unit is provided to temporarily store data corresponding to each channel on the output side or the input side of the switch unit in each direction in the PCM transmission line. A data delay control unit delays data among the data corresponding to channels and stored in the channel data storage unit. The data corresponding to a plurality of channels is output in order in the same frame and delayed by the number of frames indicated by the most delayed data corresponding to channels to provide frame correction instruction information for outputting a data string in the same frame.
摘要翻译： 在PCM传输线中的开关单元中的延迟帧校正系统用于数据通信。 提供一个通道数据存储单元，用于在PCM传输线中的每个方向上临时存储与开关单元的输出侧或输入侧相对应的每个通道的数据。 数据延迟控制单元将对应于通道的数据中的数据延迟并存储在通道数据存储单元中。 对应于多个信道的数据在相同帧中按顺序输出，并延迟由对应于信道的最延迟数据指示的帧数，以提供用于在同一帧中输出数据串的帧校正指令信息。
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5.发明授权Interface device between a network and an exchange for assembling fixed-length cell and transmitting the same 失效网络和交换机之间的接口设备，用于组装固定长度的小区并传输
公开(公告)号：US5555261A
公开(公告)日：1996-09-10
申请号：US339541
申请日：1994-11-15
CPC分类号： H04J3/0632 , H04Q11/0478 , H04L2012/5615 , H04L2012/5616 , H04L2012/5652 , H04L2012/5654 , H04L2012/5674
摘要： An internal timing information producing portion produces internal timing information IRTS1 to IRTS4 which is the timing information on a data reception clock by using a network clock C.sub.N and the data reception clock C.sub.RU. A calculator calculates the difference between the internal timing information IRTS1 to IRTS4 and the transmission timing information RRTS1 to RRTS4 contained in a received cell, and a data reception clock producing portion adjusts the timing of the data reception clock C.sub.RU so that the difference is zero and outputs the adjusted timing. An ATM cell decomposing portion outputs the user data D.sub.RU in synchronism with the data reception clock C.sub.RU which is input from the data reception clock producing portion.
摘要翻译： 内部定时信息产生部分通过使用网络时钟CN和数据接收时钟CRU，产生作为数据接收时钟的定时信息的IRTS1至IRTS4。 计算器计算内部定时信息IRTS1至IRTS4与包含在接收单元中的发送定时信息RRTS1至RRTS4之间的差异，并且数据接收时钟产生部分调整数据接收时钟CRU的定时，使得该差为零， 输出调整时间。 ATM信元分解部分与从数据接收时钟产生部分输入的数据接收时钟CRU同步地输出用户数据DRU。
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公开(公告)号：US5455824A
公开(公告)日：1995-10-03
申请号：US132044
申请日：1993-10-05
申请人： Yuzo Okuyama , Satoshi Kakuma , Yasunori Tonooka , Megumi Shibata
发明人： Yuzo Okuyama , Satoshi Kakuma , Yasunori Tonooka , Megumi Shibata
CPC分类号： H04Q3/602 , H04J3/0602 , H04J3/125 , H04Q11/0407
摘要： A message information terminating system in a switching center is connected to a plurality of remote stations by Derived Data Link interfaces and includes transmission lines connected to the same data terminal unit of the switching center, for transmitting message information containing various information such as subscriber information with communication data by framing bits between the switching center and each of said remote stations, and a message terminating equipment provided with a processing unit for analyzing the message information and disposed in a network at the switching center. The data terminal unit collects the message information from a plurality of the remote stations and transmits the message information to the message terminating equipment through the network. The message terminating equipment separates the message information from each of the remote stations, analyzes the message information, using the processing unit, and sends normal message information to a control processor in the switching center when the message terminating equipment detects a normal message.
摘要翻译： 交换中心的消息信息终端系统通过派生数据链路接口连接到多个远程站，并且包括连接到交换中心的相同数据终端单元的传输线，用于发送包含诸如用户信息的各种信息的消息信息， 通信数据通过在交换中心和每个所述远程站之间进行比特比特，以及消息终端设备，其具有用于分析消息信息并且被布置在交换中心的网络中的处理单元。 数据终端单元从多个远程站收集消息信息，并通过网络将消息信息发送到消息终端设备。 消息终端设备从每个远程站分离消息信息，使用处理单元分析消息信息，并且当消息终端设备检测到正常消息时，将正常消息信息发送到交换中心中的控制处理器。
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公开(公告)号：US5418788A
公开(公告)日：1995-05-23
申请号：US168398
申请日：1993-12-17
申请人： Yuzo Okuyama , Satoshi Kakuma
发明人： Yuzo Okuyama , Satoshi Kakuma
CPC分类号： H04J3/1641 , H04Q11/04
摘要： A multiplexer multiplexes data of data links received from respective digital lines over to an intraoffice link. A terminator extracts data of the data links received from the respective digital lines multiplexed over to a corresponding intraoffice link, and processes them in a batch. When respective data links are configured by using frame synchronization bits, e.g. at a predetermined frame timing for multiframes, the multiplexer multiplexes frame synchronization bits without shedding their synchronization pattern over to the intraoffice link, and the terminator extracts only the received data of the data links by the frame synchronization bits. In this case, on multiplexing only the frame synchronization bits from respective digital lines, the multiplexer multiplexes identification data indicating that the multiplexing timing is at the head end frames of multiframes. The terminator extracts the identification data and identifies the timing for the head end frames of the multiframes.
摘要翻译： 多路复用器将从各个数字线路接收到的数据链路的数据复用到一个局内链路。 终端器提取从相应的数字线路接收到的数据链路的数据，复用到相应的局内链路，并且批量处理它们。 当各个数据链路通过使用帧同步比特来配置时，例如， 在多帧的预定帧定时，多路复用器多路复用帧同步比特，而不将其同步模式切换到帧内链路，并且终端器仅通过帧同步比特提取数据链路的接收数据。 在这种情况下，在仅复用来自各个数字线路的帧同步位的情况下，复用器复用指示复用定时位于多帧的前端帧的识别数据。 终结器提取识别数据并识别多帧头端帧的定时。
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公开(公告)号：US06628614B2
公开(公告)日：2003-09-30
申请号：US09337061
申请日：1999-06-21
申请人： Yuzo Okuyama , Naotoshi Watanabe
发明人： Yuzo Okuyama , Naotoshi Watanabe
IPC分类号： H04J116
CPC分类号： H04L12/5602 , H04L12/5601 , H04L2012/5636 , H04L2012/5637 , H04L2012/5658 , H04L2012/5662 , H04Q11/0478
摘要： A UPC process unit judges whether an arrived cell conforms to a declared parameter. When receiving a cell which is transmitted by a GFR service, a frame process unit modifies the judgment result of the UPC process unit taking an AAL5 frame into consideration. A cell process unit discards the arrived cell based on the judgment result of the UPC process unit or the modified result.
摘要翻译： UPC处理单元判断到达的信元是否符合声明的参数。 当接收到由GFR服务发送的小区时，帧处理单元考虑考虑到AAL5帧的UPC处理单元的判断结果。 单元处理单元基于UPC处理单元的判断结果或修改结果来丢弃到达的单元。
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公开(公告)号：US5778001A
公开(公告)日：1998-07-07
申请号：US696355
申请日：1996-08-13
CPC分类号： H04J3/0632 , H04Q11/0478 , H04L2012/5615 , H04L2012/5616 , H04L2012/5652 , H04L2012/5654 , H04L2012/5674
摘要： An internal timing information producing portion produces internal timing information IRTS1 to IRTS4 which is the timing information on a data reception clock by using a network clock C.sub.N and the data reception clock C.sub.RU. A calculator calculates the difference between the internal timing information IRTS1 to IRTS4 and the transmission timing information RRTS1 to RRTS4 contained in a received cell, and a data reception clock producing portion adjusts the timing of the data reception clock C.sub.RU so that the difference is zero and outputs the adjusted timing. An ATM cell decomposing portion outputs the user data D.sub.RU in synchronism with the data reception clock C.sub.RU which is input from the data reception clock producing portion.
摘要翻译： 内部定时信息产生部分通过使用网络时钟CN和数据接收时钟CRU，产生作为数据接收时钟的定时信息的IRTS1至IRTS4。 计算器计算内部定时信息IRTS1至IRTS4与包含在接收单元中的发送定时信息RRTS1至RRTS4之间的差异，并且数据接收时钟产生部分调整数据接收时钟CRU的定时，使得该差为零， 输出调整时间。 ATM信元分解部分与从数据接收时钟产生部分输入的数据接收时钟CRU同步地输出用户数据DRU。
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公开(公告)号：US06026098A
公开(公告)日：2000-02-15
申请号：US931638
申请日：1997-09-16
申请人： Jyoei Kamoi , Tomoyuki Yamaguchi , Mikio Nakayama , Yuzo Okuyama
发明人： Jyoei Kamoi , Tomoyuki Yamaguchi , Mikio Nakayama , Yuzo Okuyama
CPC分类号： H04L49/3081 , H04J3/247 , H04Q11/0478 , H04L2012/5672
摘要： A plurality of input lines are respectively connected to separate multiplexing units that are connected in cascade by cascading lines. Select signals are transferred in parallel with fixed length packets over the cascading lines. Each separate multiplexing unit is responsive to a select signal received from the cascading line to select one of fixed length packets received over the corresponding input line and the upstream cascading line and output it over the downstream cascading line. The most downstream separate multiplexing unit provides a multiplexed output of the input lines.
摘要翻译： 多个输入线分别连接到通过级联线级联连接的分离复用单元。 选择信号通过级联线路与固定长度的数据包并行传输。 每个单独的复用单元响应于从级联线路接收的选择信号，以选择在相应输入线路和上游级联线路上接收的固定长度分组中的一个，并在下游级联线路上输出。 最下游单独复用单元提供输入线的多路复用输出。
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