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    Fabrication process of a semiconductor integrated circuit device
    1.
    发明授权
    Fabrication process of a semiconductor integrated circuit device 有权
    半导体集成电路器件的制造工艺

    公开(公告)号：US07122469B2

    公开(公告)日：2006-10-17

    申请号：US11196293

    申请日：2005-08-04

    申请人： Yoshikazu Tanabe ,  Isamu Asano ,  Makoto Yoshida ,  Naoki Yamamoto ,  Masayoshi Saito ,  Nobuyoshi Natsuaki

    发明人： Yoshikazu Tanabe ,  Isamu Asano ,  Makoto Yoshida ,  Naoki Yamamoto ,  Masayoshi Saito ,  Nobuyoshi Natsuaki

    IPC分类号： H01L21/44 ,  H01L21/31

    CPC分类号： H01L21/28247 ,  H01L21/28061 ,  H01L21/28176 ,  H01L21/32105 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823828 ,  H01L21/823857 ,  H01L27/1052 ,  H01L27/10873 ,  H01L27/10894 ,  H01L29/4941

    摘要： With a view to preventing the oxidation of a metal film at the time of light oxidation treatment after gate patterning and at the same time to making it possible to control the reproducibility of oxide film formation and homogeneity of oxide film thickness at gate side-wall end portions, in a gate processing step using a poly-metal, a gate electrode is formed by patterning a gate electrode material which has been deposited over a semiconductor wafer 1A having a gate oxide film formed thereon and has a poly-metal structure and then, the principal surface of the semiconductor wafer 1A heated to a predetermined temperature or vicinity thereof is supplied with a hydrogen gas which contains water at a low concentration, the water having been formed from hydrogen and oxygen by a catalytic action, to selectively oxidize the principal surface of the semiconductor wafer 1A, whereby the profile of the side-wall end portions of the gate electrode is improved

    摘要翻译： 为了防止栅极图案化后的光氧化处理时的金属膜的氧化，同时能够控制氧化膜形成的再现性和栅侧壁端的氧化膜厚度的均匀性 在使用多金属的栅极处理步骤中，通过对已在其上形成有栅极氧化膜的半导体晶片1A上淀积的具有多金属结构的栅电极材料进行构图来形成栅电极， 向被加热到预定温度或附近的半导体晶片1A的主表面供给含有低浓度的水的氢气，由氢和氧通过催化作用形成的水，以选择性地氧化 半导体晶片1A的主表面，从而提高了栅电极的侧壁端部的轮廓

    Fabrication process of a semiconductor integrated circuit device
    4.
    发明授权
    Fabrication process of a semiconductor integrated circuit device 有权
    半导体集成电路器件的制造工艺

    公开(公告)号：US06987069B2

    公开(公告)日：2006-01-17

    申请号：US10821842

    申请日：2004-04-12

    申请人： Yoshikazu Tanabe ,  Isamu Asano ,  Makoto Yoshida ,  Naoki Yamamoto ,  Masayoshi Saito ,  Nobuyoshi Natsuaki

    发明人： Yoshikazu Tanabe ,  Isamu Asano ,  Makoto Yoshida ,  Naoki Yamamoto ,  Masayoshi Saito ,  Nobuyoshi Natsuaki

    IPC分类号： H01L21/31

    CPC分类号： H01L21/28247 ,  H01L21/28061 ,  H01L21/28176 ,  H01L21/32105 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823828 ,  H01L21/823857 ,  H01L27/1052 ,  H01L27/10873 ,  H01L27/10894 ,  H01L29/4941

    摘要： With a view to preventing the oxidation of a metal film at the time of light oxidation treatment after gate patterning and at the same time to making it possible to control the reproducibility of oxide film formation and homogeneity of oxide film thickness at gate side-wall end portions, in a gate processing step using a poly-metal, a gate electrode is formed by patterning a gate electrode material which has been deposited over a semiconductor wafer 1A having a gate oxide film formed thereon and has a poly-metal structure and then, the principal surface of the semiconductor wafer 1A heated to a predetermined temperature or vicinity thereof is supplied with a hydrogen gas which contains water at a low concentration, the water having been formed from hydrogen and oxygen by a catalytic action, to selectively oxidize the principal surface of the semiconductor wafer 1A, whereby the profile of the side-wall end portions of the gate electrode is improved.

    摘要翻译： 为了防止栅极图案化后的光氧化处理时的金属膜的氧化，同时能够控制氧化膜形成的再现性和栅侧壁端的氧化膜厚度的均匀性 在使用多金属的栅极处理步骤中，通过对已在其上形成有栅极氧化膜的半导体晶片1A上淀积的具有多金属结构的栅电极材料进行构图来形成栅电极， 向被加热到预定温度或附近的半导体晶片1A的主表面供给含有低浓度的水的氢气，由氢和氧通过催化作用形成的水，以选择性地氧化 半导体晶片1A的主表面，从而提高了栅电极的侧壁端部的轮廓。

    Fabrication process of a semiconductor integrated circuit device
    7.
    发明授权
    Fabrication process of a semiconductor integrated circuit device 失效
    半导体集成电路器件的制造工艺

    公开(公告)号：US06197702B1

    公开(公告)日：2001-03-06

    申请号：US09086568

    申请日：1998-05-29

    申请人： Yoshikazu Tanabe ,  Isamu Asano ,  Makoto Yoshida ,  Naoki Yamamoto ,  Masayoshi Saito ,  Nobuyoshi Natsuaki

    发明人： Yoshikazu Tanabe ,  Isamu Asano ,  Makoto Yoshida ,  Naoki Yamamoto ,  Masayoshi Saito ,  Nobuyoshi Natsuaki

    IPC分类号： H01L2131

    CPC分类号： H01L21/28247 ,  H01L21/28061 ,  H01L21/28176 ,  H01L21/32105 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823828 ,  H01L21/823857 ,  H01L27/1052 ,  H01L27/10873 ,  H01L27/10894 ,  H01L29/4941

    摘要： With a view to preventing the oxidation of a metal film at the time of light oxidation treatment after gate patterning and at the same time to making it possible to control the reproducibility of oxide film formation and homogeneity of oxide film thickness at gate side-wall end portions, in a gate processing step using a poly-metal, a gate electrode is formed by patterning a gate electrode material which has been deposited over a semiconductor wafer 1A having a gate oxide film formed thereon and has a poly-metal structure and then, the principal surface of the semiconductor wafer 1A heated to a predetermined temperature or vicinity thereof is supplied with a hydrogen gas which contains water at a low concentration, the water having been formed from hydrogen and oxygen by a catalytic action, to selectively oxidize the principal surface of the semiconductor wafer 1A, whereby the profile of the side-wall end portions of the gate electrode is improved.

    摘要翻译： 为了在栅极图案化之后防止光氧化处理时的金属膜的氧化，同时可以控制氧化膜形成的再现性和栅极侧壁端的氧化膜厚度的均匀性 在使用多金属的栅极处理步骤中，通过图案化已经沉积在其上形成有栅极氧化膜的半导体晶片1A上并具有多金属结构的栅电极材料来形成栅电极， 加热到预定温度或其附近的半导体晶片1A的主表面被供给含有低浓度的水的氢气，通过催化作用由氢和氧形成的水，以选择性地氧化主表面 从而提高了栅电极的侧壁端部的形状。

    Semiconductor integrated circuit device and manufacturing method thereof
    9.
    发明授权
    Semiconductor integrated circuit device and manufacturing method thereof 有权

    公开(公告)号：US06649956B2

    公开(公告)日：2003-11-18

    申请号：US10227799

    申请日：2002-08-27

    申请人： Makoto Yoshida ,  Takahiro Kumauchi ,  Yoshitaka Tadaki ,  Isamu Asano ,  Norio Hasegawa ,  Keizo Kawakita

    发明人： Makoto Yoshida ,  Takahiro Kumauchi ,  Yoshitaka Tadaki ,  Isamu Asano ,  Norio Hasegawa ,  Keizo Kawakita

    IPC分类号： H01L2972

    CPC分类号： H01L27/10852 ,  H01L27/10817

    摘要： An active region (L) with a metal insulator semiconductor field effect transistor (MISFET) (Qs) formed therein for selection of a DRAM memory cell, which makes up a memory cell of the DRAM, is arranged to have an island-like pattern that linearly extends in an X direction on one principal surface of a semiconductor substrate (1). The memory-cell selection MISFET (Qs) has an insulated gate electrode (7) (word line WL) that extends along a Y direction on the principal surface of the semiconductor substrate (1) with the same width kept along the length thereof, which gate electrode is arranged to oppose another gate electrode (7) (word line WL) adjacent thereto at a prespecified distance or pitch that is narrower than said width. In addition, a bit line (BL) is provided overlying the memory-cell select MISFET (Qs) in a manner such that the bit line extends in the X direction on the principal surface of the semiconductor substrate (1) with the same width and opposes its neighboring bit line (BL) at a distance or pitch that is wider than said width.

    Semiconductor integrated circuit and method of fabricating the same
    10.
    发明授权
    Semiconductor integrated circuit and method of fabricating the same 有权
    半导体集成电路及其制造方法

    公开(公告)号：US06483136B1

    公开(公告)日：2002-11-19

    申请号：US09446302

    申请日：2000-04-14

    申请人： Makoto Yoshida ,  Takahiro Kumauchi ,  Yoshitaka Tadaki ,  Isamu Asano ,  Norio Hasegawa ,  Keizo Kawakita

    发明人： Makoto Yoshida ,  Takahiro Kumauchi ,  Yoshitaka Tadaki ,  Isamu Asano ,  Norio Hasegawa ,  Keizo Kawakita

    IPC分类号： H01L2972

    CPC分类号： H01L27/10852 ,  H01L27/10817

    摘要： An active region (L) with a metal insulator semiconductor field effect transistor (MISFET) (Qs) formed therein for selection of a DRAM memory cell, which makes up a memory cell of the DRAM, is arranged to have an island-like pattern that linearly extends in an X direction on one principal surface of a semiconductor substrate (1). The memory-cell selection MISFET (Qs) has an insulated gate electrode (7) (word line WL) that extends along a Y direction on the principal surface of the semiconductor substrate (1) with the same width kept along the length thereof, which gate electrode is arranged to oppose another gate electrode (7) (word line WL) adjacent thereto at a prespecified distance or pitch that is narrower than said width. In addition, a bit line (BL) is provided overlying the memory-cell select MISFET (Qs) in a manner such that the bit line extends in the X direction on the principal surface of the semiconductor substrate (1) with the same width and opposes its neighboring bit line (BL) at a distance or pitch that is wider than said width.

    摘要翻译： 在其中形成有用于选择构成DRAM的存储单元的DRAM存储单元的金属绝缘体半导体场效应晶体管（MISFET）（Qs）的有源区域（L）被布置成具有岛状图案， 在半导体衬底（1）的一个主表面上沿X方向线性地延伸。 存储单元选择MISFET（Qs）具有在半导体衬底（1）的主表面上沿着Y方向延伸的绝缘栅电极（字线WL），沿着其长度保持相同的宽度， 栅电极被布置成以比所述宽度窄的预定距离或间距与与其相邻的另一个栅电极（7）（字线WL）相对。 此外，位线（BL）以这样的方式设置在存储单元选择MISFET（Qs）上，使得位线在半导体衬底（1）的主表面上沿X方向以相同的宽度延伸，并且 以比所述宽度更宽的距离或间距来对置其相邻位线（BL）。