摘要:
The present invention provides a double-side grinder capable of grinding double-sides of an aluminum disk highly efficiently and affording a ground aluminum disk free of end-face flaw and superior in both surface accuracy and dimensional accuracy while obviating the occurrence of grinding marks extending in different directions. A rough grinding mechanism having rough grinding wheels disposed opposedly to each other is mounted, a finish grinding mechanism having finish grinding wheels disposed opposedly to each other is mounted just after the rough grinding mechanism, and a belt-like carrier having a large number of pockets formed longitudinally of the carrier with aluminum disks engaged therein is passed between the rough grinding wheels and the finish grinding wheels, thereby allowing double-sides of each aluminum disk to be subjected to rough grinding and finish grinding in a continuous manner. Moreover, work rotation braking means each comprising a braking member of rubber for pressing at least one side of an aluminum disk to brake the rotation of the disk and a coiled spring for pressing the braking member to the aluminum disk are disposed on both carrier incoming and outgoing sides of a pair of grinding wheels to brake the rotation of the aluminum disk caused by follow-up rotation thereof together with rotation of the grinding wheels when the disk gets in between the grinding wheels and also when it leaves the grinding wheels.
摘要:
A semiconductor integrated circuit includes inverters and a PMOS transistor which are disposed for a first signal, and inverters and a PMOS transistor which are disposed for a second signal substantially complementary to the first signal. By the transistors, potentials of signal lines are driven. A transistor for 1.8 V is used for each of the transistors and the inverters at the rear stage. A transistor for 3.3 V is used for each of the inverters at the front stage. With the configuration, the complementary signals are transmitted at optimum timings.
摘要:
A Silicon-On-Insulator (SOI) CMOS circuit includes a plurality of PMOS transistors connected in series to each other and at least one NMOS transistor connected to one of the PMOS transistors. The NMOS transistor has its body connected to a low reference potential having a value of ground. The SOI CMOS circuit further includes a body potential generating circuit which generates a body potential between a high reference potential and a potential obtained by subtracting a built-in potential from the high reference potential. The body potential generating circuit applies the high potential to the bodies of the PMOS transistors.
摘要翻译:绝缘体上硅绝缘体(SOI)CMOS电路包括彼此串联连接的多个PMOS晶体管和连接到PMOS晶体管之一的至少一个NMOS晶体管。 NMOS晶体管的主体连接到具有接地值的低参考电位。 SOI CMOS电路还包括体电位发生电路,其产生高参考电位和通过从高参考电位减去内置电位而获得的电位之间的体电位。 体电位产生电路将高电位施加到PMOS晶体管的主体。
摘要:
A field shield portion consisting of a kind of transistor is formed to electrically insulate an NMOS region of a memory cell from other regions. The field shield portion includes a field shield gate electrode layer, a p type region and a gate insulating film. Threshold value of this transistor is set higher than the power supply voltage, and field gate electrode layer thereof is in a floating state. It is unnecessary to provide a contact portion for applying a prescribed voltage at field shield gate electrode layer. Therefore, the region for forming the contact portion in field shield gate electrode layer can be reduced. As a result, a semiconductor device of which layout area is reduced, is provided.
摘要:
In each of basic cells (BC) arranged in array in an SOI layer, PMOS and NMOS transistors are symmetrically formed. Body regions (11) and (12) are formed to divide source/drain layers (1) and (2), respectively, and gate electrodes (3) and (4) are formed on the body regions (11) and (12) respectively to sandwich gate insulating films therebetween. The gate electrodes (3) and (4) are connected at their both ends to gate contact regions (5) to (8), respectively, and the body regions (11) and (12) are connected at their one ends to body contact regions (9) and (10), respectively. The body contact regions (9) and (10) are so arranged as to sandwich the gate contact regions (5) and (7) together with the gate electrodes (3) and (4), respectively. Being of a SOI type, the device achieves high-speed operation and low power consumption. Further, with positional relation between the body contact regions (9), (10) and the gate contact regions (5), (7), the device is capable of freely setting the transistors to be of either a gate control type or a gate fixed type. As a result, the gate array type semiconductor device achieves high-speed operation and low power consumption.
摘要:
A signal monitoring device, a signal transmission/reception device and a communication device, which realize easy acquisition of a diagnosis result and a signal value, and further realize fast acquisition of the diagnosis result. A signal monitoring device includes: a difference value calculator that time-sequentially calculates, for a signal to be monitored, a difference value between a signal value thereof and a previously set threshold; and a storage that updates and stores the time-sequentially calculated difference value in accordance with a previously set rule.
摘要:
An object of the present invention is to provide a signal monitoring device, a signal transmission/reception device and a communication device, which realize easy acquisition of a diagnosis result and a signal value, and further realize fast acquisition of the diagnosis result. A signal monitoring device (30) according to the present invention includes: a difference value calculator (12) that time-sequentially calculates, for a signal to be monitored, a difference value between a signal value thereof and a previously set threshold; and a storage (13) that updates and stores the time-sequentially calculated difference value in accordance with a previously set rule.
摘要:
A semiconductor device having an SOI structure having a contact for making steady the potential of a semiconductor substrate without involvement of an increase in the surface of the semiconductor device. In a semiconductor chip, an integrated circuit is fabricated within an internal circuit region, and a plurality of buffer circuits are fabricated within buffer regions. Wiring layers for supplying steady potential are formed in the area of the semiconductor chip other than the internal circuit region and the buffer regions; for example, at four corners of the semiconductor chip, and contacts for connecting the wiring layers and the semiconductor substrate are formed in the area of the integrated circuit which is not assigned for fabrication of integrated circuits, thus eliminating a necessity for ensuring a location specifically allocated for formation of the contacts.
摘要:
An inductor recognition method for recognizing an inductor, a layout inspection method wherein it is possible to automatically carry out a verification of a design standard, in the inductor and a process for a semiconductor device using this layout inspection method are provided. The inductor recognition method includes the step of arranging an inductor position representation mark so as to surround a design pattern of an interconnection part, which works as an inductor and has a starting point and a finishing point; the step of arranging a starting point position representation mark and a finishing point position representation mark so as to surround, respectively, regions corresponding to the starting point and the finishing point; and the step of recognizing information with respect to an inductor by means of the inductor position representation mark, the starting point position representation mark and the finishing point position representation mark.
摘要:
A Silicon-On-Insulator (SOI) CMOS circuit comprises a plurality of PMOS transistors connected in series to each other, each of the plurality of PMOS transistors having its body and gate connected to each other, and at least an NMOS transistor connected to one of the plurality of PMOS transistors, the NMOS transistor having its body connected to a low reference potential having a value of ground. The SOI CMOS circuit can further comprise a plurality of potential limiting circuits each connected between the body and gate of each of the plurality of PMOS transistors, for setting a lower limit of the potential of the body of each of the plurality of PMOS transistors to a voltage between a high reference potential and a potential obtained by subtracting a built-in potential from the high reference potential.
摘要翻译:绝缘体上硅绝缘体(SOI)CMOS电路包括彼此串联连接的多个PMOS晶体管,多个PMOS晶体管中的每一个具有彼此连接的主体和栅极,以及连接到一个的至少一个NMOS晶体管 的NMOS晶体管,其NMOS晶体管的主体连接到具有接地值的低参考电位。 SOI CMOS电路还可以包括多个限制电路,每个电位限制电路连接在多个PMOS晶体管中的每一个的主体和栅极之间,用于将多个PMOS晶体管的每个的主体的电位的下限设置为 通过从高参考电位减去内置电位而获得的高参考电位和电位之间的电压。