公开(公告)号：US20080230899A1

公开(公告)日：2008-09-25

申请号：US12053168

申请日：2008-03-21

申请人： Yoshimasa Amatatsu ,  Minoru Akaishi ,  Satoshi Onai ,  Katsuya Okabe ,  Yoshiaki Sano ,  Akira Yamane

发明人： Yoshimasa Amatatsu ,  Minoru Akaishi ,  Satoshi Onai ,  Katsuya Okabe ,  Yoshiaki Sano ,  Akira Yamane

IPC分类号： H01L23/48 ,  H01L21/44

CPC分类号： H01L24/11 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05018 ,  H01L2224/05022 ,  H01L2224/05085 ,  H01L2224/05559 ,  H01L2224/05567 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/3025

摘要： In a semiconductor device according to the present invention, a plurality of opening regions 5 to 8 are formed in an insulating film on a pad electrode 3. A metal layer 9 formed on the pad electrode 3 has a plurality of concave portions 10 to 13 formed therein by covering the opening regions 5 to 8. Moreover, in a peripheral portion at a bottom of each of the concave portions 10 to 13 in the metal layer 9, the metal layer 9 and a Cu plating layer 19 react with each other. By use of this structure, the metal reaction area serves as a current path on the pad electrode 3. Thus, a resistance value on the pad electrode 3 is reduced.

摘要翻译： 在根据本发明的半导体器件中，在焊盘电极3上的绝缘膜中形成多个开口区域5至8。 形成在焊盘电极3上的金属层9通过覆盖开口区域5〜8而形成有多个凹部10〜13。 此外，在金属层9的各凹部10〜13的底部的周边部分中，金属层9和Cu镀层19相互反应。 通过使用该结构，金属反应区域作为焊盘电极3上的电流路径。 因此，焊盘电极3上的电阻值降低。

公开(公告)号：US08076781B2

公开(公告)日：2011-12-13

申请号：US12081487

申请日：2008-04-16

申请人： Yoshimasa Amatatsu ,  Minoru Akaishi ,  Satoshi Onai ,  Katsuya Okabe ,  Yoshiaki Sano ,  Akira Yamane

发明人： Yoshimasa Amatatsu ,  Minoru Akaishi ,  Satoshi Onai ,  Katsuya Okabe ,  Yoshiaki Sano ,  Akira Yamane

IPC分类号： H01L29/43

CPC分类号： H01L21/76816 ,  H01L21/32051 ,  H01L21/76838 ,  H01L21/76843 ,  H01L21/7685 ,  H01L21/76886 ,  H01L23/5226 ,  H01L23/53223 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02166 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05096 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05548 ,  H01L2224/05554 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/11462 ,  H01L2224/1148 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2224/05552

摘要： A conventional semiconductor device has a problem that reduction of a connection resistance value between wiring layers is difficult because of an oxide film formed between the wiring layers. In a semiconductor device of this invention, a first metal layer is embeded in opening regions which connect a first wiring layer and a second wiring layer and an opening is formed in a spin coated resin film formed on the first metal layer. In the opening, a Cr layer forming a plating metal layer and a Cu plated layer are connected to each other. With this structure, the spaces among crystal grains in portions in the Cr layer on the first metal layer are wide, which causes the portions to be coarse. In the coarse portions in the Cr layer, an alloy layer formed of the second metal layer and the Cu plated layer is formed, and thus, the connection resistance value is reduced.

摘要翻译： 常规的半导体器件具有由于在布线层之间形成氧化膜而导致布线层之间的连接电阻值的降低困难的问题。 在本发明的半导体装置中，第一金属层被嵌入在连接第一布线层和第二布线层的开放区域中，并且在形成在第一金属层上的旋涂树脂膜中形成开口。 在开口中，形成镀覆金属层的Cr层和Cu镀层彼此连接。 利用这种结构，第一金属层上的Cr层中的部分中的晶粒之间的空间很宽，这使得这些部分变粗。 在Cr层的粗糙部分中，形成由第二金属层和Cu镀层形成的合金层，从而降低连接电阻值。

公开(公告)号：US08013442B2

公开(公告)日：2011-09-06

申请号：US12053168

申请日：2008-03-21

申请人： Yoshimasa Amatatsu ,  Minoru Akaishi ,  Satoshi Onai ,  Katsuya Okabe ,  Yoshiaki Sano ,  Akira Yamane

发明人： Yoshimasa Amatatsu ,  Minoru Akaishi ,  Satoshi Onai ,  Katsuya Okabe ,  Yoshiaki Sano ,  Akira Yamane

IPC分类号： H01L23/48

CPC分类号： H01L24/11 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05018 ,  H01L2224/05022 ,  H01L2224/05085 ,  H01L2224/05559 ,  H01L2224/05567 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/3025

摘要： In a semiconductor device according to the present invention, a plurality of opening regions 5 to 8 are formed in an insulating film on a pad electrode 3. A metal layer 9 formed on the pad electrode 3 has a plurality of concave portions 10 to 13 formed therein by covering the opening regions 5 to 8. Moreover, in a peripheral portion at a bottom of each of the concave portions 10 to 13 in the metal layer 9, the metal layer 9 and a Cu plating layer 19 react with each other. By use of this structure, the metal reaction area serves as a current path on the pad electrode 3. Thus, a resistance value on the pad electrode 3 is reduced.

摘要翻译： 在根据本发明的半导体器件中，在焊盘电极3上的绝缘膜中形成多个开口区域5至8.形成在焊盘电极3上的金属层9具有形成的多个凹部10至13 另外，在金属层9的各凹部10〜13的底部的周边部分中，金属层9和Cu镀层19相互反应。 通过使用这种结构，金属反应区域用作焊盘电极3上的电流路径。因此，焊盘电极3上的电阻值减小。

公开(公告)号：US20080258301A1

公开(公告)日：2008-10-23

申请号：US12081487

申请日：2008-04-16

申请人： Yoshimasa Amatatsu ,  Minoru Akaishi ,  Satoshi Onai ,  Katsuya Okabe ,  Yoshiaki Sano ,  Akira Yamane

发明人： Yoshimasa Amatatsu ,  Minoru Akaishi ,  Satoshi Onai ,  Katsuya Okabe ,  Yoshiaki Sano ,  Akira Yamane

IPC分类号： H01L23/48 ,  H01L21/44

CPC分类号： H01L21/76816 ,  H01L21/32051 ,  H01L21/76838 ,  H01L21/76843 ,  H01L21/7685 ,  H01L21/76886 ,  H01L23/5226 ,  H01L23/53223 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02166 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05096 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05548 ,  H01L2224/05554 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/11462 ,  H01L2224/1148 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2224/05552

摘要： A conventional semiconductor device has a problem that reduction of a connection resistance value between wiring layers is difficult because of an oxide film formed between the wiring layers. In a semiconductor device of this invention, a first metal layer is embeded in opening regions which connect a first wiring layer and a second wiring layer and an opening is formed in a spin coated resin film formed on the first metal layer. In the opening, a Cr layer forming a plating metal layer and a Cu plated layer are connected to each other. With this structure, the spaces among crystal grains in portions in the Cr layer on the first metal layer are wide, which causes the portions to be coarse. In the coarse portions in the Cr layer, an alloy layer formed of the second metal layer and the Cu plated layer is formed, and thus, the connection resistance value is reduced.

摘要翻译： 常规的半导体器件具有由于在布线层之间形成氧化膜而导致布线层之间的连接电阻值的降低困难的问题。 在本发明的半导体装置中，第一金属层被嵌入在连接第一布线层和第二布线层的开放区域中，并且在形成在第一金属层上的旋涂树脂膜中形成开口。 在开口中，形成镀覆金属层的Cr层和Cu镀层彼此连接。 利用这种结构，第一金属层上的Cr层中的部分中的晶粒之间的空间很宽，这使得这些部分变粗。 在Cr层的粗糙部分中，形成由第二金属层和Cu镀层形成的合金层，从而降低连接电阻值。

公开(公告)号：US08227341B2

公开(公告)日：2012-07-24

申请号：US12646173

申请日：2009-12-23

申请人： Satoshi Onai ,  Minoru Akaishi ,  Hiroshi Ishizeki ,  Yoshiaki Sano

发明人： Satoshi Onai ,  Minoru Akaishi ,  Hiroshi Ishizeki ,  Yoshiaki Sano

IPC分类号： H01L21/44 ,  H01L29/40

CPC分类号： H01L23/53238 ,  H01L24/03 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L24/85 ,  H01L2224/04042 ,  H01L2224/05083 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05556 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48463 ,  H01L2224/48644 ,  H01L2224/48655 ,  H01L2224/48664 ,  H01L2224/48844 ,  H01L2224/48855 ,  H01L2224/48864 ,  H01L2224/85 ,  H01L2224/85205 ,  H01L2924/00011 ,  H01L2924/00015 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/05042 ,  H01L2924/10253 ,  H01L2924/13091 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/01006

摘要： An object is to prevent a failure, such as a wiring separation or a crack, in an insulating film under a copper wire, in a semiconductor device formed by wire-bonding the copper wire on a portion above the copper wiring. A semiconductor device according to the present invention includes a copper wiring formed above a semiconductor substrate, a plated layer formed so as to cover a top surface and side surfaces of the copper wiring, and a copper wire which is wire-bonded on the plated layer above the copper wiring.

摘要翻译： 在通过在铜布线上的部分上引线接合铜线形成的半导体器件中，目的是防止铜线下的绝缘膜中的布线分离或裂纹等的故障。 根据本发明的半导体器件包括形成在半导体衬底上的铜布线，形成为覆盖铜布线的顶表面和侧表面的镀层和在镀层上引线接合的铜线 铜线上方。

公开(公告)号：US20100164105A1

公开(公告)日：2010-07-01

申请号：US12646173

申请日：2009-12-23

申请人： Satoshi ONAI ,  Minoru Akaishi ,  Hiroshi Ishizeki ,  Yoshiaki Sano

发明人： Satoshi ONAI ,  Minoru Akaishi ,  Hiroshi Ishizeki ,  Yoshiaki Sano

IPC分类号： H01L23/532 ,  H01L21/768

CPC分类号： H01L23/53238 ,  H01L24/03 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L24/85 ,  H01L2224/04042 ,  H01L2224/05083 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05556 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48463 ,  H01L2224/48644 ,  H01L2224/48655 ,  H01L2224/48664 ,  H01L2224/48844 ,  H01L2224/48855 ,  H01L2224/48864 ,  H01L2224/85 ,  H01L2224/85205 ,  H01L2924/00011 ,  H01L2924/00015 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/05042 ,  H01L2924/10253 ,  H01L2924/13091 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/01006

摘要： An object is to prevent a failure, such as a wiring separation or a crack, in an insulating film under a copper wire, in a semiconductor device formed by wire-bonding the copper wire on a portion above the copper wiring. A semiconductor device according to the present invention includes a copper wiring formed above a semiconductor substrate, a plated layer formed so as to cover a top surface and side surfaces of the copper wiring, and a copper wire which is wire-bonded on the plated layer above the copper wiring.

摘要翻译： 在通过在铜布线上的部分上引线接合铜线形成的半导体器件中，目的是防止铜线下的绝缘膜中的布线分离或裂纹等的故障。 根据本发明的半导体器件包括形成在半导体衬底上的铜布线，形成为覆盖铜布线的顶表面和侧表面的镀层和在镀层上引线接合的铜线 铜线上方。

公开(公告)号：US06911806B2

公开(公告)日：2005-06-28

申请号：US10734170

申请日：2003-12-15

申请人： Mitsuo Saeki ,  Hidetoshi Yano ,  Hidekiyo Ozawa ,  Seiya Kitagawa ,  Toshiyuki Matsuyama ,  Takashi Matsumoto ,  Kyuichi Takimoto ,  Yoshiaki Sano

发明人： Mitsuo Saeki ,  Hidetoshi Yano ,  Hidekiyo Ozawa ,  Seiya Kitagawa ,  Toshiyuki Matsuyama ,  Takashi Matsumoto ,  Kyuichi Takimoto ,  Yoshiaki Sano

IPC分类号： H02M3/155 ,  G05F1/40 ,  H02M1/00 ,  H02M1/36 ,  H02M3/156

CPC分类号： H02M1/36 ,  H02M3/156 ,  H02M2001/008

摘要： A direct-current to direct-current conversion (DC/DC) apparatus includes a control circuit having an error amplifier for voltage control, basing the conversion on a pulse width modulation control using an output of the error amplifier. The error amplifier inputs a voltage signal corresponding to an output voltage of a DC/DC result and a plurality of reference voltage signals. The DC/DC apparatus also includes a soft start capacitor to provide one of the plurality of reference voltage signals. The error amplifier amplifies a difference between the voltage signal corresponding to the output voltage of a DC/DC result and a voltage signal of a lower potential among the plurality of reference voltage signals and carries out the pulse width modulation control. Furthermore, the control circuit includes a circuit for discharging charges corresponding to the output voltage of the DC/DC result when a power supply to the control circuit is turned off.

摘要翻译： 直流到直流转换（DC / DC）装置包括具有用于电压控制的误差放大器的控制电路，利用误差放大器的输出根据脉宽调制控制的转换。 误差放大器输入对应于DC / DC结果和多个参考电压信号的输出电压的电压信号。 DC / DC装置还包括软启动电容器，以提供多个参考电压信号中的一个。 误差放大器放大对应于DC / DC结果的输出电压的电压信号与多个参考电压信号中较低电位的电压信号之间的差值，并执行脉宽调制控制。 此外，当控制电路的电源被断开时，控制电路包括用于放电对应于DC / DC结果的输出电压的电荷的电路。

公开(公告)号：US5474368A

公开(公告)日：1995-12-12

申请号：US110689

申请日：1993-08-23

申请人： Yoshiaki Sano

发明人： Yoshiaki Sano

IPC分类号： B60T8/58 ,  B60T8/172 ,  B60T8/174 ,  B60T8/1763 ,  B60T8/42 ,  B60T8/66

CPC分类号： B60T8/174 ,  B60T8/4266

摘要： An anti-skid braking method is provided for controlling, on the basis of a slip ratio of a wheel and an acceleration of the wheel, braking force to be applied to the wheel. The anti-skid braking method comprises the following steps: where the slip ratio is found to fall outside an appropriate range during slip ratio computation, adding differences between a limit defining the appropriate range and the respective slip ratio values so computed; and when the integral of the differences is at least equal to a predetermined value and the acceleration of the wheel is detected to be low, enhancing the control of the braking force, the control being performed based on the wheel acceleration and the slip ratio, so that the slip ratio is brought back into the appropriate range. An anti-skid braking system suitable for use in practicing the anti-skid braking method is also described.

摘要翻译： 提供一种防滑制动方法，用于基于车轮的滑移比和车轮的加速度来控制施加到车轮的制动力。 防滑制动方法包括以下步骤：在滑移率计算中发现滑移比落在适当范围之外，加上限定适当范围的限制与如此计算的各滑差比值之间的差异; 并且当差异的积分至少等于预定值并且车轮的加速度被检测为低时，增强制动力的控制，则基于车轮加速度和滑移率进行控制，因此 滑差比被恢复到适当的范围内。 还描述了适用于实施防滑制动方法的防滑制动系统。

公开(公告)号：US5036936A

公开(公告)日：1991-08-06

申请号：US405540

申请日：1989-09-11

申请人： Atsuhiro Kawano ,  Yoshiaki Sano ,  Hiroshi Umeda ,  Takeshi Nishimura ,  Yasunobu Miyata ,  Keiji Inagaki

发明人： Atsuhiro Kawano ,  Yoshiaki Sano ,  Hiroshi Umeda ,  Takeshi Nishimura ,  Yasunobu Miyata ,  Keiji Inagaki

IPC分类号： B60K31/04 ,  B60W50/00 ,  F16H61/00

CPC分类号： B60K31/047 ,  B60W2050/0057 ,  B60W2710/0605 ,  F16H2061/0081 ,  Y10S706/90 ,  Y10T477/676

摘要： A cruise control device is provided with a vehicle speed sensor for detecting the actual vehicle speed, and an electronic controller for controlling the opening of the throttle valve based on the detected vehicle speed, to bring the vehicle speed close to a target vehicle speed. The electronic controller serves to obtain a vehicle speed deviation between the target vehicle speed set by a set switch and the actual vehicle speed, select one of a P control mode, a P/D control mode and a fuzzy control mode corresponding to the magnitude of the vehicle speed deviation, and control the opening of the throttle valve. In addition to these functions, the electronic controller may additionally have the function of estimating a change in the vehicle speed provided that the current opening of the throttle valve is maintained, to obtain a correction value for the vehicle speed so that a corrected vehicle speed corrected by the correction value is used to control the opening of the throttle valve. Further, in the case of a vehicle provided with an automatic transmission, a shift diagram applied to a cruise control mode may be prepared in addition to the shift diagram for the automatic transmission itself, so that the electronic controller may have the function of effecting a shifting of the gear ratios of the automatic transmission.

摘要翻译： 巡航控制装置设置有用于检测实际车速的车速传感器和用于基于检测到的车速来控制节气门的打开的电子控制器，以使车速接近目标车速。 电子控制器用于获得由设定开关设定的目标车速与实际车速之间的车速偏差，选择P控制模式，P / D控制模式和对应于模拟控制模式的模糊控制模式 车速偏差，并控制节流阀的开度。 除了这些功能之外，如果维持节流阀的当前开度，电子控制器还可以具有估计车速的变化的功能，以获得车速的校正值，从而校正车辆速度 通过校正值来控制节流阀的开度。 此外，在设置有自动变速器的车辆的情况下，除了自动变速器本身的变速图之外，还可以准备应用于巡航控制模式的换档图，使得电子控制器可以具有实现 换档自动变速箱的齿轮比。

公开(公告)号：US4898839A

公开(公告)日：1990-02-06

申请号：US271746

申请日：1988-11-15

申请人： Chikao Fujinuma ,  Nobuyuki Sekikawa ,  Teruo Tabata ,  Tadayoshi Takada ,  Yoshiaki Sano ,  Toshimasa Sadakata

发明人： Chikao Fujinuma ,  Nobuyuki Sekikawa ,  Teruo Tabata ,  Tadayoshi Takada ,  Yoshiaki Sano ,  Toshimasa Sadakata

IPC分类号： H01L21/761 ,  H01L21/8248 ,  H01L27/06

CPC分类号： H01L21/761 ,  H01L21/8248 ,  H01L27/0658 ,  Y10S148/014

摘要： A method of manufacturing a semiconductor integrated circuit comprises the steps of: forming an epitaxial layer covering a semiconductor substrate and buried layers; forming isolation regions dividing the epitaxial layer into a plurality of islands; forming a lower electrode region of an MIS type capacitor in one of the islands; forming a base region of a vertical bipolar transistor simultaneously with or independently from the lower electrode in another island; depositing a thin dielectric layer of the MIS type capacitor on a portion of the lower electrode region; thereafter selectively diffusing impurities into the surface layer of the base region so as to form an emitter region of the vertical bipolar transistor; and forming an upper electrode of the MIS type capacitor on the thin dielectric layer.

摘要翻译： 一种制造半导体集成电路的方法包括以下步骤：形成覆盖半导体衬底和掩埋层的外延层; 形成将外延层分成多个岛的隔离区; 在其中一个岛中形成MIS型电容器的下电极区域; 在另一岛中与下电极同时或独立地形成垂直双极晶体管的基极区; 在所述下电极区域的一部分上沉积所述MIS型电容器的薄介电层; 然后选择性地将杂质扩散到基极区的表面层中，以形成垂直双极晶体管的发射极区; 以及在所述薄介电层上形成所述MIS型电容器的上电极。