公开(公告)号：US06353934B1

公开(公告)日：2002-03-12

申请号：US09464773

申请日：1999-12-16

申请人： Yoshio Tada ,  Akio Sugi ,  Satomi Fujita

发明人： Yoshio Tada ,  Akio Sugi ,  Satomi Fujita

IPC分类号： A41D102

CPC分类号： A41D1/04 ,  A41B1/00 ,  A41D27/10

摘要： A outerwear comprising of a front body cloth, a rear body cloth, right and left flank cloths having a predetermined width and right and left sleeve cloths, one edge of each right and left flank cloth is sewn to the front body cloth and the other edge of each right and left flank cloth is sewn to the rear body cloth such that each sewing line does not coincide with right and left flank lines, each of the right and left flank cloth is extended to the under-sleeve part sewn to the sleeve cloth; an elongation percentage of each of the front body cloth and the rear body cloth is set high in a horizontal direction thereof.

摘要翻译： 由前身布，后身布，具有预定宽度的右侧和左侧布以及左右袖布组成的外衣，将左右两侧布的一个边缘缝合到前身体布上，另一边缘 将每个左右侧面布缝合到后身布上，使得每个缝合线不与右侧和左侧面线重合，左右两侧布中的每一个延伸到缝合到套筒布的下套筒部分 ; 前身体布和后身体布中的每一个的伸长率在其水平方向上设定得较高。

公开(公告)号：US09087893B2

公开(公告)日：2015-07-21

申请号：US13575984

申请日：2011-01-28

申请人： Yasuhiko Onishi ,  Mutsumi Kitamura ,  Akio Sugi ,  Manabu Takei

发明人： Yasuhiko Onishi ,  Mutsumi Kitamura ,  Akio Sugi ,  Manabu Takei

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10

CPC分类号： H01L29/7802 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/66712 ,  H01L29/7813

摘要： A parallel p-n layer (20) is provided as a drift layer between an active portion and an n+ drain region (11). The parallel p-n layer (20) is formed by an n-type region (1) and a p-type region (2) being repeatedly alternately joined. An n-type high concentration region (21) is provided on a first main surface side of the n-type region (1). The n-type high concentration region (21) has an impurity concentration higher than that of an n-type low concentration region (22) provided on a second main surface side of the n-type region (1). The n-type high concentration region (21) has an impurity concentration 1.2 times or more, 3 times or less, preferably 1.5 times or more, 2.5 times or less, greater than that of the n-type low concentration region (22). Also, the n-type high concentration region (21) has one-third or less, preferably one-eighth or more, one-fourth or less, of the thickness of a region of the n-type region (1) adjacent to the p-type region (2).

摘要翻译： 在活性部分和n +漏极区域（11）之间提供平行p-n层（20）作为漂移层。 平行p-n层（20）由n型区域（1）和重复交替接合的p型区域（2）形成。 n型高浓度区域（21）设置在n型区域（1）的第一主表面侧。 n型高浓度区域（21）的杂质浓度高于设置在n型区域（1）的第二主面侧的n型低浓度区域（22）的杂质浓度。 n型高浓度区域（21）的杂质浓度比n型低浓度区域（22）的杂质浓度大1.2倍以上3倍以下，优选为1.5倍以上2.5倍以下。 此外，n型高浓度区域（21）的n区域（1）的相邻区域的厚度的三分之一以下，优选为八分之一以上，四分之一以下。 p型区域（2）。

公开(公告)号：US07365392B2

公开(公告)日：2008-04-29

申请号：US11010508

申请日：2004-12-14

申请人： Akio Sugi ,  Naoto Fujishima ,  Mutsumi Kitamura ,  Katsuya Tabuchi ,  Setsuko Wakimoto

发明人： Akio Sugi ,  Naoto Fujishima ,  Mutsumi Kitamura ,  Katsuya Tabuchi ,  Setsuko Wakimoto

IPC分类号： H01L27/00

CPC分类号： H01L29/7825 ,  H01L21/8234 ,  H01L21/8249 ,  H01L27/0623 ,  H01L27/088 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/456 ,  H01L29/66621 ,  H01L29/66659 ,  H01L29/7801 ,  H01L29/7827 ,  H01L29/7834 ,  H01L29/7835

摘要： Gate electrodes of a TLPM and gate electrodes of planar devices are formed by patterning a same polysilicon layer. Drain electrode(s) and source electrode(s) of the TLPM and drain electrodes and source electrodes of the planar devices are formed by patterning a same metal layer. Therefore, the TLPM and the planar devices can be connected electrically to each other by resulting metal wiring layers and polysilicon layers without the need for performing wire bonding on a printed circuit board.

摘要翻译： 通过图案化同一多晶硅层形成TLPM的栅电极和平面器件的栅电极。 通过对相同的金属层进行构图，形成TLPM的漏极和源极，并且平面器件的漏电极和源电极形成。 因此，TLPM和平面器件可以通过所得的金属布线层和多​​晶硅层彼此电连接，而不需要在印刷电路板上进行引线接合。

公开(公告)号：US20050062101A1

公开(公告)日：2005-03-24

申请号：US10927434

申请日：2004-08-27

申请人： Akio Sugi ,  Naoto Fujishima

发明人： Akio Sugi ,  Naoto Fujishima

IPC分类号： H01L21/762 ,  H01L21/77 ,  H01L21/84 ,  H01L27/12 ,  H01L29/417 ,  H01L29/423 ,  H01L29/739 ,  H01L29/94 ,  H01L21/3205

CPC分类号： H01L21/84 ,  H01L21/76283 ,  H01L27/1203 ,  H01L29/41766 ,  H01L29/4232 ,  H01L29/4238 ,  H01L29/7394

摘要： A semiconductor structure with device trench and a semiconductor device in the device trench, that enables realization of high integration, lowered on-resistance, reduction in switching losses and a high operation speed in a semiconductor device provided with a lateral IGBT, and that prevents malfunctions such as latchup when IGBTs or an IGBT and CMOS devices are integrated together. The structure includes an SOI substrate having a supporting substrate, an oxide film and a p−-semiconductor layer. An island-like element-forming region is isolated by a trench isolation region from surroundings. The trench isolation region includes an isolation trench with an insulation film on its inner wall. The device trench is formed in the element-forming region. A gate electrode is formed with a gate insulator film in the device trench. A collector region and an emitter region outside are provided respectively on the bottom and the outside of the device trench.

摘要翻译： 在器件沟槽中具有器件沟槽和半导体器件的半导体结构，能够实现在具有横向IGBT的半导体器件中实现高集成度，降低导通电阻，降低开关损耗以及高操作速度，并且防止故障 例如当IGBT或IGBT和CMOS器件集成在一起时闭锁。 该结构包括具有支撑衬底，氧化膜和p - 半导体层的SOI衬底。 岛状元件形成区域通过与环境的沟槽隔离区隔离。 沟槽隔离区域包括在其内壁上具有绝缘膜的隔离沟槽。 器件沟槽形成在元件形成区域中。 栅电极在器件沟槽中形成有栅极绝缘膜。 分别在器件沟槽的底部和外部设置集电极区域和外部的发射极区域。

公开(公告)号：US08378418B2

公开(公告)日：2013-02-19

申请号：US12805965

申请日：2010-08-26

申请人： Mutsumi Kitamura ,  Akio Sugi ,  Naoto Fujishima ,  Shinichiro Matsunaga

发明人： Mutsumi Kitamura ,  Akio Sugi ,  Naoto Fujishima ,  Shinichiro Matsunaga

IPC分类号： H01L29/66

CPC分类号： H01M10/4207 ,  H01L27/0629 ,  H01L29/0696 ,  H01L29/4238 ,  H01L29/781 ,  H01L29/7827 ,  H01M10/48

摘要： A bidirectional Trench Lateral Power MOSFET (TLPM) can achieve a high breakdown voltage and a low on-resistance. A plurality of straight-shaped islands having circular portions at both ends are surrounded by a trench arrangement. The islands provide first n source regions and a second n source region is formed on the outside of the islands. With such a pattern, the breakdown voltage in the case where the first n source regions are at a high potential can be higher than the breakdown voltage in the case where the second n source region is at a high potential. Alternatively, in the case of not changing the breakdown voltage, the on-resistance can be reduced.

摘要翻译： 双向沟槽横向功率MOSFET（TLPM）可实现高击穿电压和低导通电阻。 在两端具有圆形部分的多个直形岛被沟槽布置包围。 这些岛提供第一n个源区，并且在岛的外部形成第二n源区。 利用这种图案，在第二n个源极区域处于高电位的情况下，在第一n个源极区域处于高电位的情况下的击穿电压可以高于击穿电压。 或者，在不改变击穿电压的情况下，可以降低导通电阻。

公开(公告)号：US07535059B2

公开(公告)日：2009-05-19

申请号：US11564053

申请日：2006-11-28

申请人： Koh Yoshikawa ,  Akio Sugi ,  Kouta Takahashi ,  Manabu Takei ,  Haruo Nakazawa ,  Noriyuki Iwamuro

发明人： Koh Yoshikawa ,  Akio Sugi ,  Kouta Takahashi ,  Manabu Takei ,  Haruo Nakazawa ,  Noriyuki Iwamuro

IPC分类号： H01L29/76

CPC分类号： H01L29/7811 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/41741 ,  H01L29/4236 ,  H01L29/66734 ,  H01L29/7802 ,  H01L29/7813

摘要： A semiconductor device including an n-type semiconductor substrate, a p-type channel region and a junction layer provided between the n-type semiconductor substrate and the p-type channel region is disclosed. The junction layer has n-type drift regions and p-type partition regions alternately arranged in the direction in parallel with the principal surface of the n-type semiconductor substrate. The p-type partition region forming the junction layer is made to have a higher impurity concentration than the n-type drift region. This enables the semiconductor device to have an enhanced breakdown voltage and, at the same time, have a reduced on-resistance.

摘要翻译： 公开了一种包括n型半导体衬底，p型沟道区和设置在n型半导体衬底和p型沟道区之间的结层的半导体器件。 接合层具有与n型半导体衬底的主表面平行的方向交替布置的n型漂移区和p型隔离区。 形成结层的p型分隔区的杂质浓度比n型漂移区高。 这使得半导体器件具有增强的击穿电压，并且同时具有降低的导通电阻。

公开(公告)号：US20080303087A1

公开(公告)日：2008-12-11

申请号：US12149016

申请日：2008-04-24

申请人： Akio Sugi ,  Naoto Fujishima ,  Mutsumi Kitamura ,  Katsuya Tabuchi ,  Setsuko Wakimoto

发明人： Akio Sugi ,  Naoto Fujishima ,  Mutsumi Kitamura ,  Katsuya Tabuchi ,  Setsuko Wakimoto

IPC分类号： H01L27/088 ,  H01L21/8234

CPC分类号： H01L29/7825 ,  H01L21/8234 ,  H01L21/8249 ,  H01L27/0623 ,  H01L27/088 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/456 ,  H01L29/66621 ,  H01L29/66659 ,  H01L29/7801 ,  H01L29/7827 ,  H01L29/7834 ,  H01L29/7835

摘要： Gate electrodes of a TLPM and gate electrodes of planar devices are formed by patterning a same polysilicon layer. Drain electrode(s) and source electrode(s) of the TLPM and drain electrodes and source electrodes of the planar devices are formed by patterning a same metal layer. Therefore, the TLPM and the planar devices can be connected electrically to each other by resulting metal wiring layers and polysilicon layers without the need for performing wire bonding on a printed circuit board.

公开(公告)号：US20050087800A1

公开(公告)日：2005-04-28

申请号：US11010508

申请日：2004-12-14

申请人： Akio Sugi ,  Naoto Fujishima ,  Mutsumi Kitamura ,  Katsuya Tabuchi ,  Setsuko Wakimoto

发明人： Akio Sugi ,  Naoto Fujishima ,  Mutsumi Kitamura ,  Katsuya Tabuchi ,  Setsuko Wakimoto

IPC分类号： H01L21/8234 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/088 ,  H01L29/417 ,  H01L29/45 ,  H01L29/78 ,  H01L29/76

CPC分类号： H01L29/7825 ,  H01L21/8234 ,  H01L21/8249 ,  H01L27/0623 ,  H01L27/088 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/456 ,  H01L29/66621 ,  H01L29/66659 ,  H01L29/7801 ,  H01L29/7827 ,  H01L29/7834 ,  H01L29/7835

摘要： Gate electrodes of a TLPM and gate electrodes of planar devices are formed by patterning a same polysilicon layer. Drain electrode(s) and source electrode(s) of the TLPM and drain electrodes and source electrodes of the planar devices are formed by patterning a same metal layer. Therefore, the TLPM and the planar devices can be connected electrically to each other by resulting metal wiring layers and polysilicon layers without the need for performing wire bonding on a printed circuit board.

公开(公告)号：US20120126315A1

公开(公告)日：2012-05-24

申请号：US13313583

申请日：2011-12-07

申请人： Yasuhiko ONISHI ,  Akio Sugi

发明人： Yasuhiko ONISHI ,  Akio Sugi

IPC分类号： H01L29/78

CPC分类号： H01L29/7811 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/402 ,  H01L29/404 ,  H01L29/41741

摘要： A semiconductor apparatus that has a first parallel pn-layer formed between an active region and an n+-drain region. A peripheral region is provided with a second parallel pn-layer, which has a repetition pitch narrower than the repetition pitch of the first parallel pn-layer. An n−-surface region is formed between the second parallel pn-layer and a first main surface. On the first main surface side of the n−-surface region, a plurality of p-guard ring regions are formed to be separated from each other. A field plate electrode is connected electrically to the outermost p-guard ring region among the p-guard ring regions. A channel stopper electrode is connected electrically to an outermost peripheral p-region of the peripheral region.

摘要翻译： 一种半导体装置，其具有在有源区域和n + - 划分区域之间形成的第一并联pn层。 外围区域设置有第二平行pn层，其具有比第一并联pn层的重复间距窄的重复间距。 在第二平行pn层和第一主表面之间形成n表面区域。 在n面区域的第一主表面侧，形成多个p保护环区域以彼此分离。 场板电极电连接到保护环区域中的最外侧保护环区域。 通道阻挡电极电连接到周边区域的最外周边p区域。

公开(公告)号：US07256086B2

公开(公告)日：2007-08-14

申请号：US11329012

申请日：2006-01-10

申请人： Katsuya Tabuchi ,  Naoto Fujishima ,  Mutsumi Kitamura ,  Akio Sugi

发明人： Katsuya Tabuchi ,  Naoto Fujishima ,  Mutsumi Kitamura ,  Akio Sugi

IPC分类号： H01L21/336 ,  H01L21/8234

CPC分类号： H01L29/7825 ,  H01L21/823885 ,  H01L27/0922 ,  H01L29/41766 ,  H01L29/4232 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66674 ,  H01L29/7801 ,  H01L29/7809

摘要： A semiconductor device is provided that can be manufactured by a simpler process than a conventional lateral trench power MOSFET for use with an 80V breakdown voltage, and which has a lower device pitch and lower on-state resistance per unit area than a conventional lateral power MOSFET for use with a lower breakdown voltage than 80V. A gate oxide film is formed thinly along the lateral surfaces of a trench at a uniform thickness. Then, a gate oxide film is formed along the bottom surface of the trench by selective oxidation so as to be thicker than the gate oxide film on the lateral surfaces of the trench and so as to become progressively thicker from the edge of the bottom surface of the trench toward drain polysilicon.

摘要翻译： 提供了一种半导体器件，其可以通过比用于80V击穿电压的常规横向沟槽功率MOSFET更简单的工艺制造，并且其具有比常规侧向功率MOSFET更小的器件间距和每单位面积的较低导通电阻 用于低于80V的击穿电压。 沿着沟槽的侧表面以均匀的厚度薄化地形成栅氧化膜。 然后，通过选择性氧化沿着沟槽的底表面形成栅极氧化膜，以便比沟槽的侧表面上的栅极氧化膜更厚，并且从底表面的边缘逐渐变厚 沟渠朝向多晶硅排水。