公开(公告)号：US07154804B2

公开(公告)日：2006-12-26

申请号：US11377348

申请日：2006-03-17

申请人： Yoshio Takazawa ,  Toshio Yamada ,  Shinichi Ozawa ,  Takeo Kanai ,  Minoru Katoh ,  Koudou Yamauchi ,  Toshihiro Araki

发明人： Yoshio Takazawa ,  Toshio Yamada ,  Shinichi Ozawa ,  Takeo Kanai ,  Minoru Katoh ,  Koudou Yamauchi ,  Toshihiro Araki

IPC分类号： G11C7/00

CPC分类号： G11C5/14 ,  G11C7/12 ,  G11C7/22 ,  G11C17/12 ,  G11C2207/2227

摘要： A semiconductor integrated circuit has a memory which can enter active state or standby state, and the memory has voltage generation circuits for bit lines and source lines with which memory cells are connected. The voltage generation circuits make the potential of the bit lines and the potential of the source lines equal to each other in response to an instruction to transition from active state to standby state. The voltage generation circuits produce a potential difference between the bit lines and the source lines in response to an instruction to transition from standby state to active state. In standby state, the potential of the bit lines and that of the source lines are equal to each other. Therefore, sub-threshold leakage does not occur between the source and drain of each memory cell. In active state, the source line potential is not varied.

摘要翻译： 半导体集成电路具有可以进入活动状态或待机状态的存储器，并且存储器具有用于存储单元连接的位线和源极线的电压产生电路。 响应于从活动状态转换到待机状态的指令，电压产生电路使位线的电位和源极线的电位彼此相等。 响应于从待机状态转换到活动状态的指令，电压产生电路产生位线和源极线之间的电位差。 在待机状态下，位线的电位和源极线的电位彼此相等。 因此，每个存储单元的源极和漏极之间不会发生次阈值泄漏。 在活动状态下，源极线电位不变。

公开(公告)号：US07317658B2

公开(公告)日：2008-01-08

申请号：US11377351

申请日：2006-03-17

申请人： Yoshio Takazawa ,  Toshio Yamada ,  Shinichi Ozawa ,  Takeo Kanai ,  Minoru Katoh ,  Koudou Yamauchi ,  Toshihiro Araki

发明人： Yoshio Takazawa ,  Toshio Yamada ,  Shinichi Ozawa ,  Takeo Kanai ,  Minoru Katoh ,  Koudou Yamauchi ,  Toshihiro Araki

IPC分类号： G11C8/00

CPC分类号： G11C5/14 ,  G11C7/12 ,  G11C7/22 ,  G11C17/12 ,  G11C2207/2227

摘要： A semiconductor integrated circuit has a memory which can enter active state or standby state, and the memory has voltage generation circuits for bit lines and source lines with which memory cells are connected. The voltage generation circuits make the potential of the bit lines and the potential of the source lines equal to each other in response to an instruction to transition from active state to standby state. The voltage generation circuits produce a potential difference between the bit lines and the source lines in response to an instruction to transition from standby state to active state. In standby state, the potential of the bit lines and that of the source lines are equal to each other. Therefore, sub-threshold leakage does not occur between the source and drain of each memory cell. In active state, the source line potential is not varied.

摘要翻译： 半导体集成电路具有可以进入活动状态或待机状态的存储器，并且存储器具有用于存储单元连接的位线和源极线的电压产生电路。 响应于从活动状态转换到待机状态的指令，电压产生电路使位线的电位和源极线的电位彼此相等。 响应于从待机状态转换到活动状态的指令，电压产生电路产生位线和源极线之间的电位差。 在待机状态下，位线的电位和源极线的电位彼此相等。 因此，每个存储单元的源极和漏极之间不会发生次阈值泄漏。 在活动状态下，源极线电位不变。

公开(公告)号：US20060164906A1

公开(公告)日：2006-07-27

申请号：US11377351

申请日：2006-03-17

申请人： Yoshio Takazawa ,  Toshio Yamada ,  Shinichi Ozawa ,  Takeo Kanai ,  Minoru Katoh ,  Koudou Yamauchi ,  Toshihiro Araki

发明人： Yoshio Takazawa ,  Toshio Yamada ,  Shinichi Ozawa ,  Takeo Kanai ,  Minoru Katoh ,  Koudou Yamauchi ,  Toshihiro Araki

IPC分类号： G11C5/14

CPC分类号： G11C5/14 ,  G11C7/12 ,  G11C7/22 ,  G11C17/12 ,  G11C2207/2227

摘要： A semiconductor integrated circuit has a memory which can enter active state or standby state, and the memory has voltage generation circuits for bit lines and source lines with which memory cells are connected. The voltage generation circuits make the potential of the bit lines and the potential of the source lines equal to each other in response to an instruction to transition from active state to standby state. The voltage generation circuits produce a potential difference between the bit lines and the source lines in response to an instruction to transition from standby state to active state. In standby state, the potential of the bit lines and that of the source lines are equal to each other. Therefore, sub-threshold leakage does not occur between the source and drain of each memory cell. In active state, the source line potential is not varied.

公开(公告)号：US20060187734A1

公开(公告)日：2006-08-24

申请号：US11377348

申请日：2006-03-17

申请人： Yoshio Takazawa ,  Toshio Yamada ,  Shinichi Ozawa ,  Takeo Kanai ,  Minoru Katoh ,  Koudou Yamauchi ,  Toshihiro Araki

发明人： Yoshio Takazawa ,  Toshio Yamada ,  Shinichi Ozawa ,  Takeo Kanai ,  Minoru Katoh ,  Koudou Yamauchi ,  Toshihiro Araki

IPC分类号： G11C5/14

CPC分类号： G11C5/14 ,  G11C7/12 ,  G11C7/22 ,  G11C17/12 ,  G11C2207/2227

摘要： A semiconductor integrated circuit has a memory which can enter active state or standby state, and the memory has voltage generation circuits for bit lines and source lines with which memory cells are connected. The voltage generation circuits make the potential of the bit lines and the potential of the source lines equal to each other in response to an instruction to transition from active state to standby state. The voltage generation circuits produce a potential difference between the bit lines and the source lines in response to an instruction to transition from standby state to active state. In standby state, the potential of the bit lines and that of the source lines are equal to each other. Therefore, sub-threshold leakage does not occur between the source and drain of each memory cell. In active state, the source line potential is not varied.

公开(公告)号：US07046573B2

公开(公告)日：2006-05-16

申请号：US10748137

申请日：2003-12-31

申请人： Yoshio Takazawa ,  Toshio Yamada ,  Shinichi Ozawa ,  Takeo Kanai ,  Minoru Katoh ,  Koudou Yamauchi ,  Toshihiro Araki

发明人： Yoshio Takazawa ,  Toshio Yamada ,  Shinichi Ozawa ,  Takeo Kanai ,  Minoru Katoh ,  Koudou Yamauchi ,  Toshihiro Araki

IPC分类号： G11C7/00

CPC分类号： G11C5/14 ,  G11C7/12 ,  G11C7/22 ,  G11C17/12 ,  G11C2207/2227

摘要： A semiconductor integrated circuit has a memory which can enter active state or standby state, and the memory has voltage generation circuits for bit lines and source lines with which memory cells are connected. The voltage generation circuits make the potential of the bit lines and the potential of the source lines equal to each other in response to an instruction to transition from active state to standby state. The voltage generation circuits produce a potential difference between the bit lines and the source lines in response to an instruction to transition from standby state to active state. In standby state, the potential of the bit lines and that of the source lines are equal to each other. Therefore, sub-threshold leakage does not occur between the source and drain of each memory cell. In active state, the source line potential is not varied.

公开(公告)号：US07357330B2

公开(公告)日：2008-04-15

申请号：US11432378

申请日：2006-05-12

申请人： Kazuki Watanabe ,  Yutaka Nakadai ,  Shinichi Ozawa

发明人： Kazuki Watanabe ,  Yutaka Nakadai ,  Shinichi Ozawa

IPC分类号： G06K19/06

CPC分类号： G06K19/0723

摘要： A semiconductor integrated circuit device (IC) and a contactless IC card including a receiver circuit that is able to stably demodulate information signals superimposed on AC signals from an interrogator. The receiver circuit included in the IC is equipped with antenna terminals, a power supply circuit, and a filter circuit. The information signal from which a high frequency component was eliminated through the filter circuit is input via a capacitor to an inverting input terminal of an operational amplifier and a reference voltage is input to a non-inverting input terminal thereof. After the information signal is fed back through a feedback path to the non-inverting input terminal of the operational amplifier, that signal is amplified and the amplified information signal is binarised by a binarising circuit, thereby data transmitted from the interrogator is demodulated. The contactless IC card comprises an antenna coil and the IC including this receiver circuit.

摘要翻译： 一种半导体集成电路器件（IC）和非接触式IC卡，包括能够稳定地解调来自询问器的叠加在AC信号上的信息信号的接收电路。 IC中包括的接收器电路配备有天线端子，电源电路和滤波电路。 通过滤波器电路消除高频分量的信息信号通过电容器输入到运算放大器的反相输入端，并且参考电压被输入到其非反相输入端。 在通过反馈路径将信息信号反馈到运算放大器的非反相输入端之后，该信号被放大，并且放大的信息信号由二元化电路二进制化，从而从询问器发送的数据被解调。 非接触IC卡包括天线线圈和包括该接收器电路的IC。

公开(公告)号：US20100002866A1

公开(公告)日：2010-01-07

申请号：US12493690

申请日：2009-06-29

申请人： Shinichi Ozawa

发明人： Shinichi Ozawa

IPC分类号： H04M9/08

CPC分类号： H04M9/082

摘要： A voice communicating apparatus in which a far-end voice of high sound quality can be outputted from a loudspeaker and an echo which is caused by the outputted far-end voice can be accurately removed with high precision. An analog far-end voice signal supplied from a telephone unit is directly outputted from the loudspeaker and a digital detection sound signal of the far-end voice and a near-end voice detected by a microphone is delayed by a predetermined time and supplied to an arithmetic operating part.

摘要翻译： 能够从扬声器输出高音质的远端声音的语音通信装置，能够高精度地精确地去除由输出的远端语音引起的回波。 从扬声器直接输出从电话单元提供的模拟远端语音信号，并且将远端语音的数字检测声音信号和由麦克风检测到的近端声音延迟预定时间并提供给 算术运算部分。

公开(公告)号：US07044393B2

公开(公告)日：2006-05-16

申请号：US11028043

申请日：2005-01-04

申请人： Kazuki Watanabe ,  Yutaka Nakadai ,  Shinichi Ozawa

发明人： Kazuki Watanabe ,  Yutaka Nakadai ,  Shinichi Ozawa

IPC分类号： G06K19/06 ,  G06K7/00

CPC分类号： G06K19/0723

摘要： A semiconductor integrated circuit device (IC) and a contactless IC card including a receiver circuit that is able to stably demodulate information signals superimposed on AC signals from an interrogator. The receiver circuit included in the IC is equipped with antenna terminals, a power supply circuit, and a filter circuit. The information signal from which a high frequency component was eliminated through the filter circuit is input via a capacitor to an inverting input terminal of an operational amplifier and a reference voltage is input to a non-inverting input terminal thereof. After the information signal is fed back through a feedback path to the non-inverting input terminal of the operational amplifier, that signal is amplified and the amplified information signal is binarized by a binarizing circuit, thereby data transmitted from the interrogator is demodulated. The contactless IC card comprises an antenna coil and the IC including this receiver circuit.

公开(公告)号：US20050147720A1

公开(公告)日：2005-07-07

申请号：US11039791

申请日：2005-01-24

申请人： Naoyuki Yamada ,  Shinichi Ozawa ,  Naoko Kageyama ,  Hiroshi Miyano

发明人： Naoyuki Yamada ,  Shinichi Ozawa ,  Naoko Kageyama ,  Hiroshi Miyano

IPC分类号： G01N33/02 ,  G01N33/533 ,  G01N33/58 ,  G01N33/68

CPC分类号： G01N33/6827

摘要： A sample is analyzed for trace amounts of protein by dot blotting and subsequent fluorescence staining. According to this method, trace amounts of proteins such as an allergen in a food, a drink, a food additive, a medicament and feed etc. can be simply analyzed with high sensitivity. By providing the objective analysis method as described above, quantitative analysis and limit analysis of a protein contained in a sample can be performed.

摘要翻译： 通过斑点印迹和随后的荧光染色分析样品中痕量的蛋白质。 根据该方法，可以以高灵敏度简单地分析痕量的食品，饮料，食品添加剂，药物和饲料中的过敏原等蛋白质。 通过提供如上所述的客观分析方法，可以进行样品中包含的蛋白质的定量分析和极限分析。

公开(公告)号：US07111034B2

公开(公告)日：2006-09-19

申请号：US10352903

申请日：2003-01-29

申请人： Shinichi Ozawa

发明人： Shinichi Ozawa

IPC分类号： G06F7/508

CPC分类号： G06F7/508 ,  G06F2207/5063

摘要： A carry foreknowledge adder comprise an adding circuit for adding binary numbers A and B of n bits; and a plurality of carry foreknowledge circuit blocks that respectively corresponding to divisional portions obtained by dividing the A and the B through setting a unit length. Each carry foreknowledge circuit block has a plurality of arithmetic operating portions (j, i) in correspondence to each bit, that respectively receive a block carry Cin corresponding to the most significant bit in a lower the carry foreknowledge circuit block from the lower carry foreknowledge circuit block corresponding to lower divisional portion, each arithmetic operating portion arithmetically determining the carry Ci on the basis of the block carry Cin, and outputting the carry Ci to the adding circuit, and each arithmetic operating portion (j, i) has a logic circuit portion which receives the block carry Cin and is arranged on an output terminal side.

摘要翻译： 进位预知加法器包括用于加入n位的二进制数A和B的加法电路; 以及分别对应于通过设置单位长度而通过划分A和B获得的分割部分的多个进位预知电路块。 每个进位预知电路块具有对应于每个位的多个算术运算部分（j，i），分别在较低的进位预知中分别接收对应于最高有效位的中的块进位C < 电路块与较低分位部分相对应的较低进位预知电路块，每个算术运算部分基于中的块进位C 算术确定进位C i， 向加法电路输出进位C i i i，并且每个算术运算部分（j，i）都具有逻辑电路部分，其接收中的块进位C＆amp; 输出端子侧。