公开(公告)号：US20090201753A1

公开(公告)日：2009-08-13

申请号：US12320892

申请日：2009-02-06

申请人： Yoshiro Riho ,  Jun Suzuki ,  Yasuhiro Matsumoto ,  Shuichi Kubouchi ,  Hiromasa Noda ,  Yasuji Koshikawa

发明人： Yoshiro Riho ,  Jun Suzuki ,  Yasuhiro Matsumoto ,  Shuichi Kubouchi ,  Hiromasa Noda ,  Yasuji Koshikawa

IPC分类号： G11C29/00 ,  G11C8/00 ,  G11C17/16

CPC分类号： G11C8/08 ,  G11C8/10 ,  G11C29/84

摘要： There are provided are a plurality of memory mats, a sub-word driver that accesses a normal memory cell irrespective of whether a row address to which access is requested is a defective address, a sub-word driver that accesses a redundant memory cell belonging to a memory mat different from the normal memory cell indicated by the row address, when the row address is a defective address. According to the present invention, the normal memory cell and a redundant memory cell belong to memory mats different to each other, and thus the normal memory cell can be accessed concurrently with determining operation of the repair determining circuit.

摘要翻译： 提供有多个存储器垫，子字驱动器，其访问正常存储器单元，而不管请求访问的行地址是否是缺陷地址;子字驱动器，访问属于 当行地址是缺陷地址时，由行地址指示的正常存储单元不同的存储器垫。 根据本发明，正常存储单元和冗余存储单元属于彼此不同的存储器单元，从而可以在确定修复确定电路的操作的同时访问正常存储单元。

公开(公告)号：US07940583B2

公开(公告)日：2011-05-10

申请号：US12320892

申请日：2009-02-06

申请人： Yoshiro Riho ,  Jun Suzuki ,  Yasuhiro Matsumoto ,  Shuichi Kubouchi ,  Hiromasa Noda ,  Yasuji Koshikawa

发明人： Yoshiro Riho ,  Jun Suzuki ,  Yasuhiro Matsumoto ,  Shuichi Kubouchi ,  Hiromasa Noda ,  Yasuji Koshikawa

IPC分类号： G11C29/00

CPC分类号： G11C8/08 ,  G11C8/10 ,  G11C29/84

摘要： There are provided are a plurality of memory mats, a sub-word driver that accesses a normal memory cell irrespective of whether a row address to which access is requested is a defective address, a sub-word driver that accesses a redundant memory cell belonging to a memory mat different from the normal memory cell indicated by the row address, when the row address is a defective address. According to the present invention, the normal memory cell and a redundant memory cell belong to memory mats different to each other, and thus the normal memory cell can be accessed concurrently with determining operation of the repair determining circuit.

摘要翻译： 提供有多个存储器垫，子字驱动器，其访问正常存储器单元，而不管请求访问的行地址是否是缺陷地址;子字驱动器，访问属于 当行地址是缺陷地址时，由行地址指示的正常存储单元不同的存储器垫。 根据本发明，正常存储单元和冗余存储单元属于彼此不同的存储器单元，从而可以在确定修复确定电路的操作的同时访问正常存储单元。

公开(公告)号：US20100103758A1

公开(公告)日：2010-04-29

申请号：US12588730

申请日：2009-10-26

申请人： Yoshiro Riho ,  Shuichi Kubouchi

发明人： Yoshiro Riho ,  Shuichi Kubouchi

IPC分类号： G11C7/02 ,  G11C5/14

CPC分类号： G11C7/08 ,  G11C5/147 ,  G11C11/4091 ,  H01L27/10897

摘要： To provide a first power supply wiring that supplies a lower-side write potential to a sense amplifier, a second power supply wiring that supplies a higher-side write potential to the sense amplifier, a third power supply wiring that supplies an overdrive potential to the sense amplifier, and a stabilizing capacitance arranged between the first power supply wiring and the third power supply wiring. With this configuration, a capacitance value applied to the lower-side write potential and a capacitance value applied to the overdrive potential inevitably match, and thus fluctuation of the lower-side write potential and fluctuation of the overdrive potential at an initial stage of a sense operation are offset.

摘要翻译： 为了提供向读出放大器提供下侧写入电位的第一电源布线，向读出放大器提供较高侧写入电位的第二电源布线，向第一电源布线提供过驱动电位的第三电源布线 读出放大器和布置在第一电源布线和第三电源布线之间的稳定电容。 利用这种结构，施加到下侧写入电位的电容值和施加于过驱动电位的电容值不可避免地匹配，从而在感觉的初始阶段下侧写入电位的波动和过驱动电位的波动 操作被偏移。

公开(公告)号：US07940587B2

公开(公告)日：2011-05-10

申请号：US12426624

申请日：2009-04-20

申请人： Shuichi Kubouchi ,  Jun Suzuki

发明人： Shuichi Kubouchi ,  Jun Suzuki

IPC分类号： G11C29/00 ,  G11C5/06 ,  G11C7/00

CPC分类号： G11C29/38 ,  G11C7/08 ,  G11C11/401 ,  G11C11/4091 ,  G11C29/025 ,  G11C2029/1204

摘要： A semiconductor memory device comprises a memory cell array having memory cells arranged at intersections of word lines and bit lines, a first sense amplifier connected to a bit line at a predetermined position of the bit lines, a second sense amplifier connected to a bit line adjacent to the bit line at the predetermined position, a supplying circuit for supplying a predetermined voltage to each bit line connected to the first or second sense amplifier, and a sense amplifier control circuit capable of controlling the first and second sense amplifiers independently. In the semiconductor memory device, the sense amplifier control circuit performs a control in which an operation of either of the first and second sense amplifiers is stopped, the predetermined voltage is supplied to the bit line connected to the stopped sense amplifier, and the other of the first and second sense amplifiers is operated.

摘要翻译： 半导体存储器件包括存储单元阵列，存储单元布置在字线和位线的交点处，第一读出放大器连接到位线的预定位置处的位线，第二读出放大器连接到相邻的位线 到预定位置处的位线，用于向连接到第一或第二读出放大器的每个位线提供预定电压的提供电路和能够独立地控制第一和第二读出放大器的读出放大器控制电路。 在半导体存储器件中，读出放大器控制电路执行其中停止第一和第二读出放大器之一的操作的控制，将预定电压提供给连接到停止的读出放大器的位线，另一个 第一和第二读出放大器被操作。

公开(公告)号：US20090268534A1

公开(公告)日：2009-10-29

申请号：US12426624

申请日：2009-04-20

申请人： Shuichi Kubouchi ,  Jun Suzuki

发明人： Shuichi Kubouchi ,  Jun Suzuki

IPC分类号： G11C29/00 ,  G11C7/06 ,  G11C7/00

CPC分类号： G11C29/38 ,  G11C7/08 ,  G11C11/401 ,  G11C11/4091 ,  G11C29/025 ,  G11C2029/1204

摘要： A semiconductor memory device comprises a memory cell array having memory cells arranged at intersections of word lines and bit lines, a first sense amplifier connected to a bit line at a predetermined position of the bit lines, a second sense amplifier connected to a bit line adjacent to the bit line at the predetermined position, a supplying circuit for supplying a predetermined voltage to each bit line connected to the first or second sense amplifier, and a sense amplifier control circuit capable of controlling the first and second sense amplifiers independently. In the semiconductor memory device, the sense amplifier control circuit performs a control in which an operation of either of the first and second sense amplifiers is stopped, the predetermined voltage is supplied to the bit line connected to the stopped sense amplifier, and the other of the first and second sense amplifiers is operated.

摘要翻译： 半导体存储器件包括存储单元阵列，存储单元布置在字线和位线的交点处，第一读出放大器连接到位线的预定位置处的位线，第二读出放大器连接到相邻的位线 到预定位置处的位线，用于向连接到第一或第二读出放大器的每个位线提供预定电压的提供电路和能够独立地控制第一和第二读出放大器的读出放大器控制电路。 在半导体存储器件中，读出放大器控制电路执行其中停止第一和第二读出放大器之一的操作的控制，将预定电压提供给连接到停止的读出放大器的位线，另一个 第一和第二读出放大器被操作。

公开(公告)号：US20110063933A1

公开(公告)日：2011-03-17

申请号：US12923262

申请日：2010-09-10

申请人： Shuichi Kubouchi

发明人： Shuichi Kubouchi

IPC分类号： G11C8/00 ,  G11C7/00

CPC分类号： G11C17/18 ,  G11C11/408 ,  G11C17/165 ,  G11C29/824

摘要： To provided a relief-address generating circuit that generates relief address information based on plural data bits supplied in time sequence via a first terminal from outside and a programming circuit that writes into any one of fuse sets the relief address information generated by the relief-address generating circuit. With this configuration, repetition of a programming operation by the total number of the fuse sets at the maximum completes a series of write processing on relief address information. Therefore, it is possible to reduce the time required for a series of write processing on relief address information.

摘要翻译： 提供一种释放地址产生电路，其基于从外部经由第一终端以时间顺序提供的多个数据位产生释放地址信息，以及编程电路，其将保险丝集合中的救济地址信息写入 发电电路。 利用这种配置，最大限度地重复熔丝组总数的编程操作，就完成了关于浮雕地址信息的一系列写入处理。 因此，可以减少对浮雕地址信息的一系列写入处理所需的时间。

公开(公告)号：US06765844B2

公开(公告)日：2004-07-20

申请号：US10658396

申请日：2003-09-10

申请人： Hiroki Fujisawa ,  Shuichi Kubouchi ,  Koichiro Ninomiya

发明人： Hiroki Fujisawa ,  Shuichi Kubouchi ,  Koichiro Ninomiya

IPC分类号： G11C800

CPC分类号： G11C7/10 ,  G11C5/025 ,  G11C5/063 ,  G11C8/12 ,  G11C8/14 ,  G11C11/4093

摘要： Memory array areas, each including a plurality of bit lines provided along a first direction, a plurality of word lines provided along a second direction orthogonal to the first direction, and a plurality of memory cells provided in association with portions where the plurality of bit lines and the plurality of word-lines intersect, respectively, are provided in plural form in the first direction and are disposed alternately relative to sense amplifier areas. First common input/output lines connected through bit lines and first selection circuits associated with such sense amplifier areas are provided. Second common input/output lines connected through the plurality of first common input/output lines and second selection circuits corresponding to a plurality of memory arrays disposed along the first direction are provided. Each of the second common input/output lines is extended to form a signal transfer channel for transferring a signal read from each memory cell and a signal written therein.

公开(公告)号：US07085192B2

公开(公告)日：2006-08-01

申请号：US11004796

申请日：2004-12-07

申请人： Hiroki Fujisawa ,  Shuichi Kubouchi

发明人： Hiroki Fujisawa ,  Shuichi Kubouchi

IPC分类号： G11C8/00

CPC分类号： G11C7/109 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4082 ,  G11C11/4093

摘要： In a semiconductor integrated circuit device, a write command decoder decodes a write command and outputs decode pulses. A command counter circuit counts the decode pulses as the number of commands. A latch circuit latches the write aDDRess in response to a count output from the command counter circuit. A latency counter circuit counts a latency in response to the decode pulses. The semiconductor integrated circuit device further includes a circuit for turning on a column selection control signal when the count value of the latency counter circuit exceeds a predetermined latency value and a circuit for outputting the aDDRess latched by the latch circuit as a column aDDRess in response to the column selection control signal being turned on. The semiconductor integrated circuit device performs a write operation to the column aDDRess in response to the column selection control signal being turned on.

摘要翻译： 在半导体集成电路装置中，写命令解码器对写命令进行解码并输出译码脉冲。 命令计数器电路将解码脉冲计数为命令数。 锁存电路根据命令计数器电路的计数输出锁存写入数据。 延迟计数器电路响应于解码脉冲对等待时间进行计数。 半导体集成电路装置还包括：当等待时间计数器电路的计数值超过预定等待时间值时，用于接通列选择控制信号的电路，以及用于响应于第二个锁存电路输出由锁存电路锁存的DDRess作为列dDessess的电路 列选择控制信号被接通。 半导体集成电路装置响应于列选择控制信号被导通而对列aDDRess执行写操作。

公开(公告)号：US06665203B2

公开(公告)日：2003-12-16

申请号：US09866623

申请日：2001-05-30

申请人： Hiroki Fujisawa ,  Shuichi Kubouchi ,  Koichiro Ninomiya

发明人： Hiroki Fujisawa ,  Shuichi Kubouchi ,  Koichiro Ninomiya

IPC分类号： G11C502

CPC分类号： G11C7/10 ,  G11C5/025 ,  G11C5/063 ,  G11C8/12 ,  G11C8/14 ,  G11C11/4093

摘要： Memory array areas, each including a plurality of bit lines provided along a first direction, a plurality of word lines provided along a second direction orthogonal to the first direction, and a plurality of memory cells provided in association with portions where the plurality of bit lines and the plurality of word-lines intersect, respectively, are provided in plural form in the first direction and are disposed alternately relative to sense amplifier areas. First common input/output lines connected through bit lines and first selection circuits associated with such sense amplifier areas are provided. Second common input/output lines connected through the plurality of first common input/output lines and second selection circuits corresponding to a plurality of memory arrays disposed along the first direction are provided. Each of the second common input/output lines is extended to form a signal transfer channel for transferring a signal read from each memory cell and a signal written therein.

摘要翻译： 存储器阵列区域，每个存储器阵列区域包括沿着第一方向提供的多个位线，沿着与第一方向正交的第二方向设置的多个字线;以及多个存储器单元，其与多个位线 并且多个字线分别以第一方向以多个形式相交并且相对于读出放大器区域交替设置。 提供了通过位线连接的第一公共输入/输出线和与这种读出放大器区域相关联的第一选择电路。 提供了通过多个第一公共输入/输出线连接的第二公共输入/输出线和对应于沿着第一方向设置的多个存储器阵列的第二选择电路。 第二公共输入/输出线中的每一个被扩展以形成用于传送从每个存储单元读取的信号和写入其中的信号的信号传送通道。

公开(公告)号：US09543037B2

公开(公告)日：2017-01-10

申请号：US13296437

申请日：2011-11-15

申请人： Shuichi Kubouchi ,  Daiki Nakashima

发明人： Shuichi Kubouchi ,  Daiki Nakashima

IPC分类号： G11C17/18 ,  G11C29/00

CPC分类号： G11C17/18 ,  G11C29/785 ,  G11C29/789

摘要： To provide an electrical fuse that is connected to a detection node via a selective transistor, a precharge transistor that precharges the detection node in a state where the selective transistor is off; a bias transistor that passes a bias current to the detection node in a state where the selective transistor is on and the precharge transistor is off, and a detection circuit that detects a potential of the detection node in a state where the bias current is flowing into the detection node, wherein the bias transistor reduces an amount of the bias current in a stepwise manner or a continuous manner.

摘要翻译： 提供通过选择晶体管连接到检测节点的电熔丝，预选电晶体管，其在选择晶体管截止的状态下预充电检测节点; 偏置晶体管，其在选择晶体管导通并且预充电晶体管截止的状态下将偏置电流传递到检测节点;以及检测电路，其在偏置电流流入的状态下检测检测节点的电位 所述检测节点，其中所述偏置晶体管以逐步方式或连续方式减少所述偏置电流的量。