公开(公告)号：US08675438B2

公开(公告)日：2014-03-18

申请号：US14017080

申请日：2013-09-03

申请人： Kwang Sook Noh ,  Young Hun Seo ,  Jong Hyun Choi

发明人： Kwang Sook Noh ,  Young Hun Seo ,  Jong Hyun Choi

IPC分类号： G11C7/00

CPC分类号： G11C11/402 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/40626 ,  G11C2211/4061

摘要： An integrated circuit memory device includes a refresh control circuit that generates an internal memory refresh command signal having a period that is changed relative to a period of an external memory refresh command signal received by the memory device. This change in the period of the internal memory refresh command may be in response to detecting a change in temperature of the memory device. In particular, the refresh control circuit is configured so that the period of the internal memory refresh command signal is increased in response to detecting a reduction in temperature of the memory device.

摘要翻译： 集成电路存储器件包括刷新控制电路，该刷新控制电路产生具有相对于由存储器件接收的外部存储刷新命令信号的周期而改变的周期的内部存储器刷新命令信号。 内部存储器刷新命令的周期中的这种变化可以响应于检测到存储器件的温度变化。 特别地，刷新控制电路被配置为使得响应于检测到存储器件的温度降低而使内部存储器刷新命令信号的周期增加。

公开(公告)号：US07224012B2

公开(公告)日：2007-05-29

申请号：US10747111

申请日：2003-12-30

申请人： Young Hun Seo

发明人： Young Hun Seo

IPC分类号： H01L21/8234 ,  H01L21/8242 ,  H01L21/8244 ,  H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L28/60 ,  H01L27/0805

摘要： A metal/insulator/metal capacitor and a fabrication method thereof are presented. The method includes forming a first electrode on an insulation film; forming a side wall made of insulating material on a side surface of the first electrode; forming an interlayer insulation film on the top surface of the insulation film including the first electrode and the side wall; forming a via hole to expose the first electrode by selectively etching the interlayer insulation film such that an edge area at which a side surface and a bottom of the via hole intersect is positioned on a top surface of the side wall; forming a dielectric layer on an inner wall of the via hole; forming a second electrode on the dielectric layer such that the via hole is filled; and forming a metal wire on the second electrode such that the metal wire is electrically connected to the second electrode.

摘要翻译： 提出了一种金属/绝缘体/金属电容器及其制造方法。 该方法包括在绝缘膜上形成第一电极; 在所述第一电极的侧表面上形成由绝缘材料制成的侧壁; 在包括第一电极和侧壁的绝缘膜的顶表面上形成层间绝缘膜; 形成通孔，以通过选择性地蚀刻层间绝缘膜来露出第一电极，使得通孔的侧表面和底部相交的边缘区域位于侧壁的顶表面上; 在所述通孔的内壁上形成电介质层; 在所述电介质层上形成第二电极，使得所述通孔被填充; 以及在所述第二电极上形成金属线，使得所述金属线电连接到所述第二电极。

公开(公告)号：US06998324B2

公开(公告)日：2006-02-14

申请号：US10750251

申请日：2003-12-31

申请人： Young Hun Seo

发明人： Young Hun Seo

IPC分类号： H01L21/762

CPC分类号： H01L21/76232 ,  H01L21/76264 ,  H01L21/76283

摘要： Example methods of fabricating a silicon on insulator substrate are disclosed. One example method may include forming a plurality of trenches on a substrate, forming an insulation layer on the trenches, removing a portion of the insulation layer formed on the trenches to partially expose the substrate, and forming a silicon on insulator film in the substrate via the exposed portions of the substrate.

摘要翻译： 公开了制造绝缘体上硅衬底的示例性方法。 一个示例性方法可以包括在衬底上形成多个沟槽，在沟槽上形成绝缘层，去除在沟槽上形成的绝缘层的一部分以部分地暴露衬底，以及在衬底中形成绝缘体上硅膜，通过 衬底的暴露部分。

公开(公告)号：US07371656B2

公开(公告)日：2008-05-13

申请号：US11024439

申请日：2004-12-30

申请人： Young Hun Seo

发明人： Young Hun Seo

IPC分类号： H01L21/76

CPC分类号： H01L21/76224

摘要： A method for forming a STI of a semiconductor device includes steps of sequentially forming a pad oxide film and a pad nitride film on the semiconductor device and carrying out a pattern process PR; etching the pad oxide film and the nitride film and carrying out a cleaning process; selectively growing epitaxial silicon; and carrying out liner oxidation on the epitaxial silicon and carrying out CMP so as to form an oxidation fill and STI.

摘要翻译： 一种用于形成半导体器件的STI的方法包括以下步骤：在半导体器件上顺序形成衬垫氧化物膜和衬垫氮化物膜，并执行图案处理PR; 蚀刻衬垫氧化膜和氮化物膜并进行清洁处理; 选择性生长外延硅; 并在外延硅上进行衬里氧化并进行CMP以形成氧化填充物和STI。

公开(公告)号：US06727157B2

公开(公告)日：2004-04-27

申请号：US10657082

申请日：2003-09-09

申请人： Young Hun Seo

发明人： Young Hun Seo

IPC分类号： H01L218242

CPC分类号： H01L21/764 ,  H01L21/76229

摘要： In fabricating a shallow trench isolation (STI), a silicon oxide layer, a silicon nitride layer and a moat pattern is sequentially deposited on a silicon substrate. Next, the silicon nitride layer and the silicon oxide layer is etched using the moat pattern as a mask to thereby partially expose the silicon substrate and then the moat pattern is removed. Ion implanting process is performed into the silicon substrate using the silicon nitride layer as a mask, adjusting a dose of an implanted ion and an implant energy, to thereby form an isolation region. And then, the isolation region to form a porous silicon and to form an air gap in the porous silicon is anodized, wherein a porosity of the porous silicon is determined by the dose of the implanted ion. Next, the porous silicon is oxidized through an oxidation process. Finally, the silicon nitride layer is removed.

公开(公告)号：US20080185676A1

公开(公告)日：2008-08-07

申请号：US12078967

申请日：2008-04-09

申请人： Young Hun Seo

发明人： Young Hun Seo

IPC分类号： H01L29/00 ,  H01L21/76

CPC分类号： H01L21/76224

摘要： A method for forming a STI of a semiconductor device includes steps of sequentially forming a pad oxide film and a pad nitride film on the semiconductor device and carrying out a pattern process PR; etching the pad oxide film and the nitride film and carrying out a cleaning process; selectively growing epitaxial silicon; and carrying out liner oxidation on the epitaxial silicon and carrying out CMP so as to form an oxidation fill and STI.

公开(公告)号：US07148117B2

公开(公告)日：2006-12-12

申请号：US11026232

申请日：2004-12-29

申请人： Young Hun Seo

发明人： Young Hun Seo

IPC分类号： H01L21/20

CPC分类号： H01L21/76232

摘要： Methods for forming STI structures in semiconductor devices are disclosed. A disclosed method comprises: forming a buffer oxide layer on a silicon substrate; implanting ions into the entire surface of the resulting structure and removing the buffer oxide layer; depositing a gate oxide layer, a polysilicon layer and a nitride layer, forming a photoresist pattern; forming the trench of the STI structure by perform an etching process using the photoresist pattern as an etching mask; forming a thin oxide layer inside the trench and on the nitride layer on the entire surface of the resulting structure; filling the trench with an insulating layer; planarizing the insulating layer by performing a CMP process using the nitride layer as an etching stop layer; performing a recessing process to etch the planarized insulating layer and the thin oxide layer on the trench to a predetermined depth; forming a photoresist pattern on the nitride layer; and forming the gate electrodes by performing an etching process using the photoresist pattern as a mask pattern.

摘要翻译： 公开了在半导体器件中形成STI结构的方法。 所公开的方法包括：在硅衬底上形成缓冲氧化物层; 将离子注入所得结构的整个表面并除去缓冲氧化物层; 沉积栅极氧化物层，多晶硅层和氮化物层，形成光致抗蚀剂图案; 通过使用光致抗蚀剂图案作为蚀刻掩模进行蚀刻工艺来形成STI结构的沟槽; 在所述结构的整个表面上在所述沟槽内和所述氮化物层上形成薄氧化物层; 用绝缘层填充沟槽; 通过使用氮化物层作为蚀刻停止层进行CMP处理来平坦化绝缘层; 执行凹陷处理以将沟槽上的平坦化绝缘层和薄氧化物层蚀刻到预定深度; 在氮化物层上形成光致抗蚀剂图案; 以及通过使用光致抗蚀剂图案作为掩模图案进行蚀刻处理来形成栅电极。

公开(公告)号：US06955990B2

公开(公告)日：2005-10-18

申请号：US10750245

申请日：2003-12-31

申请人： Young Hun Seo

发明人： Young Hun Seo

IPC分类号： H01L21/28 ,  H01L21/3213 ,  H01L21/302 ,  H01L21/461

CPC分类号： H01L21/28114 ,  H01L21/28123 ,  H01L21/32137 ,  H01L21/32139

摘要： Methods for forming a gate in a semiconductor device are disclosed. In an example method, the gate is formed such that the CD of an upper portion of the gate is greater than the CD of a lower portion of the gate by performing multiple etching processes. In an illustrated example, the etching processes are performed in three stages, (i.e., a first dry etching process for etching the upper portion, a second dry etching process for etching the lower portion and a third dry etching) under three different process conditions, thereby causing a sidewall profile of the gate to have a two-layered structure.

摘要翻译： 公开了在半导体器件中形成栅极的方法。 在示例性方法中，通过执行多次蚀刻工艺，形成门，使得栅极的上部的CD大于栅极的下部的CD。 在图示的例子中，在三个不同的工艺条件下，分三个阶段进行蚀刻处理（即蚀刻上部的第一干蚀刻工艺，用于蚀刻下部的第二干蚀刻工艺和第三干蚀刻） 从而导致栅极的侧壁轮廓具有两层结构。