SEMICONDUCOTR MEMORY DEVICE INCLUDING NON-VOLATILE MEMORY CELL ARRAY
    3.
    发明申请
    SEMICONDUCOTR MEMORY DEVICE INCLUDING NON-VOLATILE MEMORY CELL ARRAY 有权
    包括非易失性存储器单元阵列的SEMICONDUCOTR存储器件

    公开(公告)号:US20140223257A1

    公开(公告)日:2014-08-07

    申请号:US14165820

    申请日:2014-01-28

    IPC分类号: G06F11/10

    摘要: A semiconductor memory device that may correct error data using an error correction circuit is disclosed. The semiconductor memory device may include a DRAM cell array, a parity generator, a nonvolatile memory cell array and an error correction circuit. The parity generator is configured to generate a first set of parity bits having at least one bit based on input data. The nonvolatile memory cell array may store the input data and the first set of parity bits corresponding to the input data, and to output first data corresponding to the input data, and a second set of parity bits corresponding to the first set of parity bits. The error correction circuit is configured to generate second data as corrected data based on the first data.

    摘要翻译: 公开了可以使用纠错电路校正错误数据的半导体存储器件。 半导体存储器件可以包括DRAM单元阵列,奇偶校验发生器,非易失性存储单元阵列和纠错电路。 奇偶校验发生器被配置为基于输入数据生成具有至少一个位的第一组奇偶校验位。 非易失性存储单元阵列可以存储对应于输入数据的输入数据和第一组奇偶校验位,并且输出与输入数据相对应的第一数据,以及对应于第一组奇偶校验位的第二组奇偶校验位。 误差校正电路被配置为基于第一数据生成作为校正数据的第二数据。