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    Systems having a maximum sleep mode and method of operating the same
    1.
    发明授权
    Systems having a maximum sleep mode and method of operating the same 有权
    具有最大睡眠模式的系统及其操作方法

    公开(公告)号：US09547360B2

    公开(公告)日：2017-01-17

    申请号：US14091912

    申请日：2013-11-27

    申请人： Young-Jin Park ,  Won-Seok Lee ,  Il-Guy Jung

    发明人： Young-Jin Park ,  Won-Seok Lee ,  Il-Guy Jung

    IPC分类号： G06F1/32

    CPC分类号： G06F1/3275 ,  G06F1/3209 ,  G06F1/3225 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D50/20

    摘要： A main memory system includes a main memory device including a first memory device implemented with a volatile memory and a second memory device implemented with a non-volatile memory, the main memory system being configured such that, when entering a sleep mode, the memory device reads a portion of data stored in the first memory device to store the read data in the second memory device, and, after the portion of data is read, the first memory device and the second memory device are powered off.

    摘要翻译： 主存储器系统包括主存储器件，其包括实施有易失性存储器的第一存储器件和由非易失性存储器实现的第二存储器件，所述主存储器系统被配置为使得当进入休眠模式时，存储器件 读取存储在第一存储器件中的数据的一部分以将读取的数据存储在第二存储器件中，并且在数据的部分被读取之后，第一存储器件和第二存储器件被断电。

    Memory card and memory storage device using the same
    4.
    发明授权
    Memory card and memory storage device using the same 失效
    存储卡和存储设备使用相同

    公开(公告)号：US08055844B2

    公开(公告)日：2011-11-08

    申请号：US12314320

    申请日：2008-12-08

    申请人： Won-Seok Lee ,  Jong-Keun Ahn

    发明人： Won-Seok Lee ,  Jong-Keun Ahn

    IPC分类号： G06F12/00

    CPC分类号： G06F13/387 ,  G06F12/06 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

    摘要： A memory card and a memory storage device using the memory card may be provided. The memory card may include a host connector, a memory controller connected to the host connector and enabled or disabled in response to a capacity expansion signal, a non-volatile memory connected to the memory controller, a memory connector configured to connect to the memory controller and the non-volatile memory, and a capacity expansion switch configured to generate the capacity expansion signal. Accordingly, when the memory cards are connected to increase storage capacity, only a memory controller of one memory card may operate, thereby reducing power consumption.

    摘要翻译： 可以提供使用存储卡的存储卡和存储器存储装置。 存储卡可以包括主机连接器，连接到主机连接器并且响应于容量扩展信号而被启用或禁用的存储器控​​制器，连接到存储器控制器的非易失性存储器，被配置为连接到存储器控制器的存储器连接器 和非易失性存储器，以及容量扩展开关，其被配置为生成容量扩展信号。 因此，当存储卡被连接以增加存储容量时，只有一个存储卡的存储器控​​制器可以操作，从而降低功耗。

    Memory devices and memory systems having the same
    5.
    发明申请
    Memory devices and memory systems having the same 有权
    具有相同的存储器件和存储器系统

    公开(公告)号：US20080080240A1

    公开(公告)日：2008-04-03

    申请号：US11902424

    申请日：2007-09-21

    申请人： Kwang-Jin Lee ,  Won-Seok Lee ,  Choong-Keun Kwak

    发明人： Kwang-Jin Lee ,  Won-Seok Lee ,  Choong-Keun Kwak

    IPC分类号： G11C16/00

    CPC分类号： H01L27/10802 ,  G11C7/00 ,  G11C7/10 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1084 ,  G11C11/4063 ,  H01L21/84 ,  H01L27/10844 ,  H01L27/1203 ,  H01L29/7841

    摘要： A non volatile memory device and a memory system having the same are disclosed. The non volatile memory device may include a memory cell array having a plurality of non volatile memory cells, a DRAM interface for exchanging data, a command and an address with an external device, a controller for selecting one of the memory cells in response to the address and performing a control operation for one of outputting data of the selected memory cell to the external device in response to the command and storing data received from the external device, and a DRAM buffer memory. The DRAM buffer memory has dynamic memory cells, and each of the dynamic memory cells has one transistor with a floating body.

    摘要翻译： 公开了一种非易失性存储器件和具有该非易失性存储器件的存储器系统。 非易失性存储器件可以包括具有多个非易失性存储器单元的存储器单元阵列，用于交换数据的DRAM接口，与外部设备的命令和地址，用于响应于所述存储器单元选择所述存储器单元中的一个的控制器 对所述存储器单元的数据的输出响应于所述命令并存储从所述外部设备接收的数据以及DRAM缓冲存储器，对所述存储单元的数据进行输出的地址和执行控制操作。 DRAM缓冲存储器具有动态存储单元，并且每个动态存储单元具有一个具有浮体的晶体管。

    Memory device having read charge control, write charge control and floating or precharge circuits
    6.
    发明授权
    Memory device having read charge control, write charge control and floating or precharge circuits 失效
    具有读取充电控制，写入充电控制和浮置或预充电电路的存储器件

    公开(公告)号：US06643201B2

    公开(公告)日：2003-11-04

    申请号：US10205838

    申请日：2002-07-26

    申请人： Won-Seok Lee ,  Chang-Yong Lee ,  Jung-Bae Lee ,  Won-Chang Jung

    发明人： Won-Seok Lee ,  Chang-Yong Lee ,  Jung-Bae Lee ,  Won-Chang Jung

    IPC分类号： G11C700

    CPC分类号： G11C7/1069 ,  G11C7/065 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/1078 ,  G11C7/1096 ,  G11C7/12

    摘要： A memory charging circuit includes a read charge control circuit controlled according to a read control signal and an address value. A write charge control circuit is controlled according to a write control signal and the same or a different address value. Charging to and charging from the same data IO lines is controlled using the read charge amplifier circuit and the write charge amplifier circuit. A column select line circuit can be configured into a first arrangement where a first output is activated according to a read control signal and an address and a second output is activated according to a write control signal and the same or a different address. In a second arrangement, the first output is activated according to an address and either the read control signal or the write control signal.

    摘要翻译： 存储器充电电路包括根据读取控制信号和地址值控制的读取充电控制电路。 写入充电控制电路根据写入控制信号和相同或不同的地址值进行控制。 使用读取的电荷放大器电路和写入电荷放大器电路来控制对相同数据IO线的充电和充电。 列选择线路电路可以被配置成根据读控制信号和地址激活第一输出的第一布置，并且根据写控制信号和相同或不同的地址来激活第二输出。 在第二布置中，根据地址和读控制信号或写控制信号来激活第一输出。

    Semiconductor memory device and data error detection and correction method of the same
    7.
    发明授权
    Semiconductor memory device and data error detection and correction method of the same 有权
    半导体存储器件和数据错误检测与校正方法相同

    公开(公告)号：US08190968B2

    公开(公告)日：2012-05-29

    申请号：US13099640

    申请日：2011-05-03

    申请人： Kwang-Jin Lee ,  Won-Seok Lee ,  Du-Eung Kim

    发明人： Kwang-Jin Lee ,  Won-Seok Lee ,  Du-Eung Kim

    IPC分类号： H03M13/00

    CPC分类号： G06F11/1008 ,  G06F11/1076 ,  G11C8/04 ,  G11C8/12

    摘要： A semiconductor memory device includes a memory cell array, a mode setting circuit, a parity data generation unit, and a data error detection and correction unit. The memory cell array has a plurality of first memory banks for storing normal data, and a predetermined number of second memory banks less than the number of the first memory banks for storing parity data according to control of a first flag signal. The mode setting circuit sets the first flag signal and a second flag signal controlling based on whether a separate memory bank is used to store the parity data in the second memory banks. The parity data generation unit receives normal write data during a write operation, generates parity data with respect to the normal write data in response to the second flag signal, and outputs the normal data and the parity data. The data error detection and correction unit receives normal read data and parity read data read from the memory cell array during a read operation, detects errors of the normal read data in response to the second flag signal, corrects the normal read data when the errors are detected, and outputs the corrected read data.

    摘要翻译： 半导体存储器件包括存储单元阵列，模式设置电路，奇偶校验数据生成单元和数据错误检测和校正单元。 存储单元阵列具有用于存储正常数据的多个第一存储体和小于根据第一标志信号的控制存储奇偶校验数据的第一存储体的数量的预定数量的第二存储体。 模式设置电路基于是否使用单独的存储体来存储第二存储体中的奇偶校验数据来设置第一标志信号和第二标志信号。 奇偶校验数据生成单元在写入操作期间接收正常写入数据，响应于第二标志信号生成相对于正常写入数据的奇偶校验数据，并输出正常数据和奇偶校验数据。 数据错误检测和校正单元在读取操作期间接收从存储单元阵列读取的正常读取数据和奇偶校验读取数据，响应于第二标志信号检测正常读取数据的错误，当错误为 检测并输出校正的读取数据。

    Memory card with removable cover
    8.
    发明授权
    Memory card with removable cover 失效
    带可移动盖的记忆卡

    公开(公告)号：US08151052B2

    公开(公告)日：2012-04-03

    申请号：US12314600

    申请日：2008-12-12

    申请人： Won-Seok Lee

    发明人： Won-Seok Lee

    IPC分类号： G06F12/00

    CPC分类号： H01L25/18 ,  H01L23/49855 ,  H01L25/0655 ,  H01L2224/16 ,  H01L2224/16145 ,  H05K1/111 ,  H05K1/181 ,  H05K2201/10159 ,  H05K2201/10515 ,  Y02P70/611

    摘要： The memory card includes a memory controller covered by a main body, a first non-volatile memory, a memory interface configured to transfer a signal between the memory controller and the first non-volatile memory, and a cover coupled to the main body and removeably covering the first memory and the memory interface. Here, the memory interface includes a connection detector configured to generate a connection detector signal when sensing that a package including a second non-volatile memory is added.

    摘要翻译： 存储卡包括由主体覆盖的存储器控​​制器，第一非易失性存储器，被配置为在存储器控制器和第一非易失性存储器之间传送信号的存储器接口以及耦合到主体并可移除的盖子 涵盖了第一个内存和内存接口。 这里，存储器接口包括连接检测器，其被配置为当感测到包括第二非易失性存储器的包装被添加时产生连接检测器信号。

    Semiconductor memory device and data error detection and correction method of the same
    9.
    发明授权
    Semiconductor memory device and data error detection and correction method of the same 失效
    半导体存储器件和数据错误检测与校正方法相同

    公开(公告)号：US07949928B2

    公开(公告)日：2011-05-24

    申请号：US11773214

    申请日：2007-07-03

    申请人： Kwang-Jin Lee ,  Won-Seok Lee ,  Du-Eung Kim

    发明人： Kwang-Jin Lee ,  Won-Seok Lee ,  Du-Eung Kim

    IPC分类号： G11C29/00

    CPC分类号： G06F11/1008 ,  G06F11/1076 ,  G11C8/04 ,  G11C8/12

    摘要： A semiconductor memory device includes a memory cell array, a mode setting circuit, a parity data generation unit, and a data error detection and correction unit. The memory cell array has a plurality of first memory banks for storing normal data, and a predetermined number of second memory banks less than the number of the first memory banks for storing parity data according to control of a first flag signal. The mode setting circuit sets the first flag signal and a second flag signal controlling based on whether a separate memory bank is used to store the parity data in the second memory banks. The parity data generation unit receives normal write data during a write operation, generates parity data with respect to the normal write data in response to the second flag signal, and outputs the normal data and the parity data. The data error detection and correction unit receives normal read data and parity read data read from the memory cell array during a read operation, detects errors of the normal read data in response to the second flag signal, corrects the normal read data when the errors are detected, and outputs the corrected read data.

    摘要翻译： 半导体存储器件包括存储单元阵列，模式设置电路，奇偶校验数据生成单元和数据错误检测和校正单元。 存储单元阵列具有用于存储正常数据的多个第一存储体和小于根据第一标志信号的控制存储奇偶校验数据的第一存储体的数量的预定数量的第二存储体。 模式设置电路基于是否使用单独的存储体来存储第二存储体中的奇偶校验数据来设置第一标志信号和第二标志信号。 奇偶校验数据生成单元在写入操作期间接收正常写入数据，响应于第二标志信号生成相对于正常写入数据的奇偶校验数据，并输出正常数据和奇偶校验数据。 数据错误检测和校正单元在读取操作期间接收从存储单元阵列读取的正常读取数据和奇偶校验读取数据，响应于第二标志信号检测正常读取数据的错误，当错误为 检测并输出校正的读取数据。

    Input circuit of a non-volatile semiconductor memory device
    10.
    发明授权
    Input circuit of a non-volatile semiconductor memory device 有权
    非易失性半导体存储器件的输入电路

    公开(公告)号：US07710791B2

    公开(公告)日：2010-05-04

    申请号：US11984145

    申请日：2007-11-14

    申请人： Kwang-jin Lee ,  Won-Seok Lee ,  Qi Wang ,  Hye-Jin Kim ,  Joon Yong Choi

    发明人： Kwang-jin Lee ,  Won-Seok Lee ,  Qi Wang ,  Hye-Jin Kim ,  Joon Yong Choi

    IPC分类号： G11C7/10 ,  G11C8/06 ,  G11C7/22 ,  G11C8/18

    CPC分类号： G11C7/1078 ,  G11C7/1084 ,  G11C7/225 ,  G11C16/10

    摘要： A non-volatile semiconductor memory device may include a memory cell array that may include a plurality of memory transistors; a input circuit that may control a voltage level of an internal reference voltage and a delay time of an internal clock signal in response to an MRS trim code or an electric fuse trim code, and that may generate a first buffered input signal; a column gate that may gate the first buffered input signal in response to a decoded column address signal; and a sense amplifier that may amplify an output signal of the memory cell array to output to the column gate, and that may receive an output signal of the column gate to output to the memory cell array. The non-volatile semiconductor memory device may properly buffer an input signal of a small swing range.

    摘要翻译： 非易失性半导体存储器件可以包括可以包括多个存储晶体管的存储单元阵列; 输入电路，其可以响应于MRS修剪代码或电熔丝修剪代码来控制内部参考电压的电压电平和内部时钟信号的延迟时间，并且可以产生第一缓冲输入信号; 列门，其可以响应于解码列地址信号而选通第一缓冲输入信号; 以及读出放大器，其可以放大存储单元阵列的输出信号以输出到列门，并且可以接收列门的输出信号以输出到存储器单元阵列。 非易失性半导体存储器件可以适当地缓冲小摆动范围的输入信号。