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公开(公告)号：US07541624B2
公开(公告)日：2009-06-02
申请号：US10624038
申请日：2003-07-21
IPC分类号： H01L21/00
CPC分类号： H01L29/66318 , H01L29/0821 , H01L29/41708 , H01L29/42304 , H01L29/7371
摘要： A method for fabricating a bipolar transistor includes forming collector, base, and emitter semiconductor layers on a substrate such that the layers form a vertical sequence with respect to an adjacent surface of the substrate. The method includes etching away a portion of a top one of the semiconductor layers to expose a portion of the base semiconductor layer and then, growing semiconductor on the exposed portion of the base layer. The top one of the semiconductor layers is the layer of the sequence that is located farthest from the substrate. The growing causes grown semiconductor to laterally surround a vertical portion of the top one of the semiconductor layers.
摘要翻译： 制造双极晶体管的方法包括在基板上形成集电极，基极和发射极半导体层，使得这些层相对于基板的相邻表面形成垂直的顺序。 该方法包括蚀刻远离半导体层顶部的一部分以露出基底半导体层的一部分，然后在基底层的暴露部分上生长半导体。 半导体层中的顶部之一是距离衬底最远的序列层。 生长的原因使半导体横向围绕半导体层的顶部的垂直部分。
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公开(公告)号：US20090029536A1
公开(公告)日：2009-01-29
申请号：US12286239
申请日：2008-09-29
申请人： Young-Kai Chen , Lay-Lay Chua , Vincent Etienne Houtsma , Rose Fasano Kopf , Andreas Leven , Chun-Ting Liu , Wei-Jer Sung , Yang Yang
发明人： Young-Kai Chen , Lay-Lay Chua , Vincent Etienne Houtsma , Rose Fasano Kopf , Andreas Leven , Chun-Ting Liu , Wei-Jer Sung , Yang Yang
IPC分类号： H01L21/425
CPC分类号： H01L29/66318 , H01L29/7371
摘要： A method for fabricating a bipolar transistor includes forming a vertical sequence of semiconductor layers, forming an implant mask on the last formed semiconductor layer, and implanting dopant ions into a portion of one or more of the semiconductor layers. The sequence of semiconductor layers includes a collector layer, a base layer that is in contact with the collector layer, and an emitter layer that is in contact with the base layer. The implanting uses a process in which the implant mask stops dopant ions from penetrating into a portion of the sequence of layers.
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公开(公告)号：US06911716B2
公开(公告)日：2005-06-28
申请号：US10243369
申请日：2002-09-13
申请人： Young-Kai Chen , Lay-Lay Chua , Vincent Etienne Houtsma , Rose Fasano Kopf , Andreas Leven , Chun-Ting Liu , Wei-Jer Sung , Yang Yang
发明人： Young-Kai Chen , Lay-Lay Chua , Vincent Etienne Houtsma , Rose Fasano Kopf , Andreas Leven , Chun-Ting Liu , Wei-Jer Sung , Yang Yang
IPC分类号： H01L21/331 , H01L29/737 , H01L27/082
CPC分类号： H01L29/66318 , H01L29/7371
摘要： A method for fabricating a bipolar transistor includes forming a vertical sequence of semiconductor layers, forming an implant mask on the last formed semiconductor layer, and implanting dopant ions into a portion of one or more of the semiconductor layers. The sequence of semiconductor layers includes a collector layer, a base layer that is in contact with the collector layer, and an emitter layer that is in contact with the base layer. The implanting uses a process in which the implant mask stops dopant ions from penetrating into a portion of the sequence of layers.
摘要翻译： 一种用于制造双极晶体管的方法，包括形成垂直的半导体层序列，在最后形成的半导体层上形成注入掩模，以及将掺杂离子注入到一个或多个半导体层的一部分中。 半导体层的序列包括集电极层，与集电极层接触的基极层和与基极层接触的发射极层。 植入使用其中植入掩模阻止掺杂剂离子渗入层序列的一部分的过程。
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公开(公告)号：US07595249B2
公开(公告)日：2009-09-29
申请号：US12286239
申请日：2008-09-29
申请人： Young-Kai Chen , Lay-Lay Chua , Vincent Etienne Houtsma , Rose Fasano Kopf , Andreas Leven , Chun-Ting Liu , Wei-Jer Sung , Yang Yang
发明人： Young-Kai Chen , Lay-Lay Chua , Vincent Etienne Houtsma , Rose Fasano Kopf , Andreas Leven , Chun-Ting Liu , Wei-Jer Sung , Yang Yang
IPC分类号： H01L21/331 , H01L21/8222
CPC分类号： H01L29/66318 , H01L29/7371
摘要： A method for fabricating a bipolar transistor includes forming a vertical sequence of semiconductor layers, forming an implant mask on the last formed semiconductor layer, and implanting dopant ions into a portion of one or more of the semiconductor layers. The sequence of semiconductor layers includes a collector layer, a base layer that is in contact with the collector layer, and an emitter layer that is in contact with the base layer. The implanting uses a process in which the implant mask stops dopant ions from penetrating into a portion of the sequence of layers.
摘要翻译： 一种用于制造双极晶体管的方法，包括形成垂直的半导体层序列，在最后形成的半导体层上形成注入掩模，以及将掺杂离子注入到一个或多个半导体层的一部分中。 半导体层的序列包括集电极层，与集电极层接触的基极层和与基极层接触的发射极层。 植入使用其中植入掩模阻止掺杂剂离子渗入层序列的一部分的过程。
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5.发明授权Alignment techniques for photolithography utilizing multiple photoresist layers 失效利用多个光致抗蚀剂层的光刻对准技术
公开(公告)号：US6042975A
公开(公告)日：2000-03-28
申请号：US111534
申请日：1998-07-08
IPC分类号： G03F9/00 , H01L21/027 , H01L21/285 , H01L21/335
CPC分类号： H01L29/66462 , G03F9/708 , G03F9/7084 , H01L21/0274 , H01L21/28587
摘要： The specification describes a photolithography process using multiple exposures to form z-dimension patterns. Multiple exposures at different thickness levels are made using photomasks aligned with a latent image of alignment marks formed during the first exposure. The latent image is visible to the alignment system of commercial steppers.
摘要翻译： 本说明书描述了使用多次曝光形成z维图案的光刻工艺。 使用与在第一次曝光期间形成的对准标记的潜像对准的光掩模进行不同厚度级别的多次曝光。 潜像对于商业步进机的对准系统是可见的。
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公开(公告)号：US06855613B1
公开(公告)日：2005-02-15
申请号：US09433204
申请日：1999-11-04
IPC分类号： H01L21/331 , H01L31/328
CPC分类号： H01L29/66318
摘要： A method of fabricating a III-V heterostructure semiconductor device. The method includes the steps of forming at least one conductive post overlying a semiconductor region to form a structure, encapsulating the structure and the conductive post to form a planarized cured passivation layer, and exposing the conductive post through the planarized cured passivation layer to form the semiconductor device.
摘要翻译： 一种制造III-V异质结构半导体器件的方法。 该方法包括以下步骤：形成覆盖半导体区域的至少一个导电柱以形成结构，封装该结构和导电柱以形成平坦化的固化钝化层，以及使导电柱穿过平坦化的固化钝化层，形成 半导体器件。
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公开(公告)号：US6165859A
公开(公告)日：2000-12-26
申请号：US255845
申请日：1999-02-23
IPC分类号： H01L21/331 , H01L29/45 , H01L29/737
CPC分类号： H01L29/66318 , H01L29/452 , H01L29/7371
摘要： The specification describes a metal contact material optimized for diffused contacts to the buried emitter-base junction in DHBT devices. The metal contact material is a multilayer structure of Pd--Pt--Au which gives the required critical diffusion properties for low resistance contacts to the buried base layer without shorting to the collector layer.
摘要翻译： 该说明书描述了针对DHBT器件中的掩埋发射极 - 基极结的扩散接触而优化的金属接触材料。 金属接触材料是Pd-Pt-Au的多层结构，其给出了对掩埋基底层的低电阻接触所需的临界扩散特性，而不会与集电极层短路。
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公开(公告)号：US5907165A
公开(公告)日：1999-05-25
申请号：US71006
申请日：1998-05-01
IPC分类号： H01L21/331 , H01L29/45 , H01L29/737 , H01L31/0328 , H01L31/0336 , H01L31/072 , H01L31/109
CPC分类号： H01L29/66318 , H01L29/452 , H01L29/7371
摘要： The specification describes a metal contact material optimized for diffused contacts to the buried emitter-base junction in DHBT devices. The metal contact material is a multilayer structure of Pd-Pt-Au which gives the required critical diffusion properties for low resistance contacts to the buried base layer without shorting to the collector layer.
摘要翻译： 该说明书描述了针对DHBT器件中的掩埋发射极 - 基极结的扩散接触而优化的金属接触材料。 金属接触材料是Pd-Pt-Au的多层结构，其给出了对掩埋基底层的低电阻接触所需的临界扩散特性，而不会与集电极层短路。
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9.发明授权Method of manufacturing schottky gate transistor utilizing alignment techniques with multiple photoresist layers 有权利用具有多个光致抗蚀剂层的对准技术制造肖特基栅极晶体管的方法
公开(公告)号：US6139995A
公开(公告)日：2000-10-31
申请号：US523210
申请日：2000-03-10
IPC分类号： G03F9/00 , H01L21/027 , H01L21/285 , H01L21/335
CPC分类号： H01L29/66462 , G03F9/708 , G03F9/7084 , H01L21/0274 , H01L21/28587
摘要： The specification describes a photolithography process using multiple exposures to form z-dimension patterns. Multiple exposures at different thickness levels are made using photomasks aligned with a latent image of alignment marks formed during the first exposure. The latent image is visible to the alignment system of commercial steppers.
摘要翻译： 本说明书描述了使用多次曝光形成z维图案的光刻工艺。 使用与在第一次曝光期间形成的对准标记的潜像对准的光掩模进行不同厚度级别的多次曝光。 潜像对于商业步进机的对准系统是可见的。
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公开(公告)号：US06294018B1
公开(公告)日：2001-09-25
申请号：US09396035
申请日：1999-09-15
申请人： Robert Alan Hamm , Rose Fasano Kopf , Christopher James Pinzone , Robert William Ryan , Alaric Tate
发明人： Robert Alan Hamm , Rose Fasano Kopf , Christopher James Pinzone , Robert William Ryan , Alaric Tate
IPC分类号： C30B2504
CPC分类号： H01L29/66318 , H01L23/544 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： The specification describes a lithographic technique in which alignment marks are defined in a first semiconductor layer and the alignment marks are then covered with a protective SiO2 layer. After subsequent semiconductor layer growth steps, which selectively deposit on the former semiconductor layer but not on the protective layer, the alignment marks remain undistorted and visible to the exposure tool for subsequent processing.
摘要翻译： 本说明书描述了一种光刻技术，其中对准标记被限定在第一半导体层中，并且对准标记然后被保护性SiO 2层覆盖。 在随后的半导体层生长步骤之后，其选择性地沉积在前半导体层上但不在保护层上，对准标记保持不变，并且对于曝光工具可见，用于后续处理。
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