公开(公告)号：US08254201B2

公开(公告)日：2012-08-28

申请号：US12797791

申请日：2010-06-10

申请人： Young-Soo Sohn ,  Kwang-Il Park ,  Kyoung-Ho Kim ,  Seung-Jun Bae

发明人： Young-Soo Sohn ,  Kwang-Il Park ,  Kyoung-Ho Kim ,  Seung-Jun Bae

IPC分类号： G11C8/18 ,  G11C7/10

CPC分类号： G11C7/22 ,  G11C7/1078 ,  G11C7/1084 ,  G11C8/18 ,  G11C2207/2227 ,  G11C2207/2272

摘要： A semiconductor memory device includes a memory cell array, a controller, and a data input/output (I/O) unit. The memory cell array includes a plurality of memory cells and is configured to store data. The controller is configured to enable a write clock signal in response to an active command when a write latency of the semiconductor device is less than a reference write latency and disable the write clock signal during a disabling period in which read data is output from the semiconductor device. The data I/O unit is configured to receive data in response to the write clock signal and output the data to the memory cell array.

摘要翻译： 半导体存储器件包括存储单元阵列，控制器和数据输入/输出（I / O）单元。 存储单元阵列包括多个存储单元，并被配置为存储数据。 当半导体器件的写入延迟小于参考写入延迟并且在从半导体输出读取数据的禁用期间禁止写入时钟信号时，控制器被配置为响应于有效命令来使能写入时钟信号 设备。 数据I / O单元被配置为响应于写时钟信号接收数据并将数据输出到存储单元阵列。

公开(公告)号：US20100329041A1

公开(公告)日：2010-12-30

申请号：US12797791

申请日：2010-06-10

申请人： Young-Soo SOHN ,  Kwang-IL Park ,  Kyoung-Ho Kim ,  Seung-Jun Bae

发明人： Young-Soo SOHN ,  Kwang-IL Park ,  Kyoung-Ho Kim ,  Seung-Jun Bae

IPC分类号： G11C7/10 ,  G11C8/18

CPC分类号： G11C7/22 ,  G11C7/1078 ,  G11C7/1084 ,  G11C8/18 ,  G11C2207/2227 ,  G11C2207/2272

摘要： A semiconductor memory device includes a memory cell array, a controller, and a data input/output (I/O) unit. The memory cell array includes a plurality of memory cells and is configured to store data. The controller is configured to enable a write clock signal in response to an active command when a write latency of the semiconductor device is less than a reference write latency and disable the write clock signal during a disabling period in which read data is output from the semiconductor device. The data I/O unit is configured to receive data in response to the write clock signal and output the data to the memory cell array.

摘要翻译： 半导体存储器件包括存储单元阵列，控制器和数据输入/输出（I / O）单元。 存储单元阵列包括多个存储单元，并被配置为存储数据。 当半导体器件的写入延迟小于参考写入延迟并且在从半导体输出读取数据的禁用期间禁止写入时钟信号时，控制器被配置为响应于有效命令来使能写入时钟信号 设备。 数据I / O单元被配置为响应于写时钟信号接收数据并将数据输出到存储单元阵列。

公开(公告)号：US20120127810A1

公开(公告)日：2012-05-24

申请号：US13360093

申请日：2012-01-27

申请人： Dae-Hyun Kim ,  Kwang-il Park ,  Kyoung-Ho Kim ,  Hyun-Jin Kim ,  Hye-Ran Kim

发明人： Dae-Hyun Kim ,  Kwang-il Park ,  Kyoung-Ho Kim ,  Hyun-Jin Kim ,  Hye-Ran Kim

IPC分类号： G11C8/18 ,  G11C7/00

CPC分类号： G11C8/18 ,  G11C7/08 ,  G11C8/12 ,  G11C11/4076 ,  G11C11/4091

摘要： Example embodiments provide a semiconductor memory device that may include: a cell array arranged in pluralities of rows and columns; and a sense amplifier conducting writing and reading operations to the cell array in response to writing and reading commands in correspondence with an access time, which may be variable in period. The sense amplifier adjusts pulse widths of write-in and read-out data in accordance with a period of the access time.

摘要翻译： 示例性实施例提供半导体存储器件，其可以包括：布置成多行和列的单元阵列; 以及响应于写入和读取对应于在周期可变的访问时间的访问时间，对单元阵列执行写入和读取操作的读出放大器。 读出放大器根据访问时间的周期来调整写入和读出数据的脉冲宽度。

公开(公告)号：US20080126822A1

公开(公告)日：2008-05-29

申请号：US11986917

申请日：2007-11-27

申请人： Kyoung-Ho Kim ,  Kwang-Il Park

发明人： Kyoung-Ho Kim ,  Kwang-Il Park

IPC分类号： G06F1/04 ,  G06F12/06

CPC分类号： G11C7/1078 ,  G11C7/1006 ,  G11C7/1087 ,  G11C7/1093 ,  G11C7/22 ,  G11C7/222 ,  G11C2207/107

摘要： An apparatus for aligning input data in a semiconductor device includes at least one alignment block and a decision block. The at least one alignment block is for aligning serial input data into groups of parallel data synchronized to at least one divided data strobe signal for increasing margin between the maximum and minimum tDQSS values. The decision block is for selecting one of the groups of parallel data as valid data in response to synchronization information generated for removing any invalid data in the serial input data resulting from a write gap.

摘要翻译： 用于对准半导体器件中的输入数据的装置包括至少一个对准块和判定块。 所述至少一个对准块用于将串行输入数据对准到与至少一个分割数据选通信号同步的并行数据组，以增加最大和最小tDQSS值之间的余量。 所述决定块用于响应于产生的同步信息来选择并行数据组中的一个作为有效数据，以消除由写入间隙产生的串行输入数据中的任何无效数据。

公开(公告)号：US20090268528A1

公开(公告)日：2009-10-29

申请号：US12385121

申请日：2009-03-31

申请人： Dae-Hyun Kim ,  Kwang-il Park ,  Kyoung-Ho Kim ,  Hyun-Jin Kim ,  Hye-Ran Kim

发明人： Dae-Hyun Kim ,  Kwang-il Park ,  Kyoung-Ho Kim ,  Hyun-Jin Kim ,  Hye-Ran Kim

IPC分类号： G11C7/00 ,  G11C8/00

CPC分类号： G11C8/18 ,  G11C7/08 ,  G11C8/12 ,  G11C11/4076 ,  G11C11/4091

摘要： Example embodiments provide a semiconductor memory device that may include: a cell array arranged in pluralities of rows and columns; and a sense amplifier conducting writing and reading operations to the cell array in response to writing and reading commands in correspondence with an access time, which may be variable in period. The sense amplifier adjusts pulse widths of write-in and read-out data in accordance with a period of the access time.

摘要翻译： 示例性实施例提供半导体存储器件，其可以包括：布置成多行和列的单元阵列; 以及响应于写入和读取对应于在周期可变的访问时间的访问时间，对单元阵列执行写入和读取操作的读出放大器。 读出放大器根据访问时间的周期来调整写入和读出数据的脉冲宽度。

公开(公告)号：US07975162B2

公开(公告)日：2011-07-05

申请号：US11986917

申请日：2007-11-27

申请人： Kyoung-Ho Kim ,  Kwang-Il Park

发明人： Kyoung-Ho Kim ,  Kwang-Il Park

IPC分类号： G06F1/00 ,  G11C7/00 ,  G11C8/00

CPC分类号： G11C7/1078 ,  G11C7/1006 ,  G11C7/1087 ,  G11C7/1093 ,  G11C7/22 ,  G11C7/222 ,  G11C2207/107

摘要： An apparatus for aligning input data in a semiconductor device includes at least one alignment block and a decision block. The at least one alignment block is for aligning serial input data into groups of parallel data synchronized to at least one divided data strobe signal for increasing margin between the maximum and minimum tDQSS values. The decision block is for selecting one of the groups of parallel data as valid data in response to synchronization information generated for removing any invalid data in the serial input data resulting from a write gap.

摘要翻译： 用于对准半导体器件中的输入数据的装置包括至少一个对准块和判定块。 所述至少一个对准块用于将串行输入数据对准到与至少一个分割数据选通信号同步的并行数据组，以增加最大和最小tDQSS值之间的余量。 所述决定块用于响应于产生的同步信息来选择并行数据组中的一个作为有效数据，以消除由写入间隙产生的串行输入数据中的任何无效数据。

公开(公告)号：US08422333B2

公开(公告)日：2013-04-16

申请号：US13360093

申请日：2012-01-27

申请人： Dae-Hyun Kim ,  Kwang-il Park ,  Kyoung-Ho Kim ,  Hyun-Jin Kim ,  Hye-Ran Kim

发明人： Dae-Hyun Kim ,  Kwang-il Park ,  Kyoung-Ho Kim ,  Hyun-Jin Kim ,  Hye-Ran Kim

IPC分类号： G11C8/00 ,  G11C8/18

CPC分类号： G11C8/18 ,  G11C7/08 ,  G11C8/12 ,  G11C11/4076 ,  G11C11/4091

摘要： Example embodiments provide a semiconductor memory device that may include: a cell array arranged in pluralities of rows and columns; and a sense amplifier conducting writing and reading operations to the cell array in response to writing and reading commands in correspondence with an access time, which may be variable in period. The sense amplifier adjusts pulse widths of write-in and read-out data in accordance with a period of the access time.

公开(公告)号：US08125847B2

公开(公告)日：2012-02-28

申请号：US12385121

申请日：2009-03-31

申请人： Dae-Hyun Kim ,  Kwang-il Park ,  Kyoung-Ho Kim ,  Hyun-Jin Kim ,  Hye-Ran Kim

发明人： Dae-Hyun Kim ,  Kwang-il Park ,  Kyoung-Ho Kim ,  Hyun-Jin Kim ,  Hye-Ran Kim

IPC分类号： G11C8/00 ,  G11C8/18

CPC分类号： G11C8/18 ,  G11C7/08 ,  G11C8/12 ,  G11C11/4076 ,  G11C11/4091

摘要： Example embodiments provide a semiconductor memory device that may include: a cell array arranged in pluralities of rows and columns; and a sense amplifier conducting writing and reading operations to the cell array in response to writing and reading commands in correspondence with an access time, which may be variable in period. The sense amplifier adjusts pulse widths of write-in and read-out data in accordance with a period of the access time.

摘要翻译： 示例性实施例提供半导体存储器件，其可以包括：布置成多行和列的单元阵列; 以及响应于写入和读取对应于在周期可变的访问时间的访问时间，对单元阵列执行写入和读取操作的读出放大器。 读出放大器根据访问时间的周期来调整写入和读出数据的脉冲宽度。

公开(公告)号：US20080035991A1

公开(公告)日：2008-02-14

申请号：US11696541

申请日：2007-04-04

申请人： Sang-Hyeon Lee ,  Kyoung-Ho Kim

发明人： Sang-Hyeon Lee ,  Kyoung-Ho Kim

IPC分类号： H01L31/00

CPC分类号： H01L27/10876 ,  H01L27/10823

摘要： A semiconductor device includes an upper gate trench crossing an active region of a semiconductor substrate, a lower gate trench overlapping the upper gate trench at both ends, disposed at a lower level than the upper gate trench, and having a smaller width than the upper gate trench and wherein the lower gate trench is spaced apart from sidewalls of the upper gate trench. The semiconductor device further includes a gate pattern partially covering the bottom of the upper gate trench between the sidewall of the upper gate trench and the lower gate trench, filling the lower gate trench, and covering sidewalls of the active region adjacent to the bottom and sidewalls of the lower gate trench.

摘要翻译： 半导体器件包括与半导体衬底的有源区交叉的上栅极沟槽，与两栅极沟槽重叠的下栅极沟槽，其位于比上栅极沟槽低的位置处，并且具有比上栅极更小的宽度 沟槽，并且其中所述下栅极沟槽与所述上栅极沟槽的侧壁间隔开。 半导体器件还包括栅极图案，部分地覆盖上栅极沟槽的侧壁和下栅极沟槽之间的上栅极沟槽的底部，填充下栅极沟槽，并且覆盖邻近底部和侧壁的有源区的侧壁 的下栅极沟槽。

公开(公告)号：US20070291247A1

公开(公告)日：2007-12-20

申请号：US11804469

申请日：2007-05-18

申请人： Kyoung-Ho Kim ,  Jae-Hyun Sung

发明人： Kyoung-Ho Kim ,  Jae-Hyun Sung

IPC分类号： G03B27/72

CPC分类号： G03B27/54 ,  G03B27/42 ,  G03F7/2028

摘要： In an apparatus for performing an edge exposure process on an edge portion of a photoresist film that is formed on a semiconductor wafer, light provided from a light source is formed to have a ring shape corresponding to a shape of an edge portion of the wafer by an optical unit. The ring-shaped light is irradiated onto the edge portion of the wafer through a ring lens. Thus, the light efficiency is improved. Further, since there is no need to rotate the wafer, a side surface profile of the photoresist film is improved.

摘要翻译： 在对形成在半导体晶片上的光致抗蚀剂膜的边缘部分进行边缘曝光处理的装置中，从光源提供的光由具有与晶片的边缘部分形状对应的环状形成， 光学单元。 环状光通过环形透镜照射在晶片的边缘部分上。 因此，光效率提高。 此外，由于不需要旋转晶片，光致抗蚀剂膜的侧表面轮廓得到改善。