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    SOI semiconductor integrated circuit for eliminating floating body effects in SOI MOSFETs and method of fabricating the same
    1.
    发明授权
    SOI semiconductor integrated circuit for eliminating floating body effects in SOI MOSFETs and method of fabricating the same 有权
    用于消除SOI MOSFET中的浮体效应的SOI半导体集成电路及其制造方法

    公开(公告)号：US06498370B1

    公开(公告)日：2002-12-24

    申请号：US09695341

    申请日：2000-10-24

    申请人： Young-Wug Kim ,  Byung-Sun Kim ,  Hee-Sung Kang ,  Young-Gun Ko ,  Sung-Bae Park

    发明人： Young-Wug Kim ,  Byung-Sun Kim ,  Hee-Sung Kang ,  Young-Gun Ko ,  Sung-Bae Park

    IPC分类号： H01L2701

    CPC分类号： H01L29/78615

    摘要： A silicon-on-insulator (SOD integrated circuit and a method of fabricating the SOI integrated circuit are provided. At least one isolated transistor active region and a body line are formed on an SOI substrate. The transistor active region and the body line are surrounded by an isolation layer which is in contact with a buried insulating layer of the SOI substrate. A portion of the sidewall of the transistor active region is extended to the body line. Thus, the transistor active region is electrically connected to the body line through a body extension. The body extension is covered with a body insulating layer. An insulated gate pattern is formed over the transistor active region, and one end of the gate pattern is overlapped with the body insulating layer.

    摘要翻译： 提供绝缘体上硅（SOD集成电路和制造SOI集成电路的方法），在SOI衬底上形成至少一个隔离晶体管有源区和体线，晶体管有源区和体线被包围 通过与SOI衬底的埋置绝缘层接触的隔离层，将晶体管有源区的侧壁的一部分延伸到体线，由此，晶体管有源区域通过a 主体延伸部由主体绝缘层覆盖，在晶体管有源区域上形成绝缘栅极图案，栅极图案的一端与主体绝缘层重叠。

    SOI semiconductor integrated circuit for eliminating floating body effects in SOI MOSFETs and method of fabricating the same
    2.
    发明授权
    SOI semiconductor integrated circuit for eliminating floating body effects in SOI MOSFETs and method of fabricating the same 有权
    用于消除SOI MOSFET中的浮体效应的SOI半导体集成电路及其制造方法

    公开(公告)号：US06703280B2

    公开(公告)日：2004-03-09

    申请号：US10330404

    申请日：2002-12-27

    申请人： Young-Wug Kim ,  Byung-Sun Kim ,  Hee-Sung Kang ,  Young-Gun Ko ,  Sung-Bae Park ,  Min-Su Kim ,  Kwang-Il Kim

    发明人： Young-Wug Kim ,  Byung-Sun Kim ,  Hee-Sung Kang ,  Young-Gun Ko ,  Sung-Bae Park ,  Min-Su Kim ,  Kwang-Il Kim

    IPC分类号： H01L218244

    CPC分类号： H01L29/78615

    摘要： A silicon-on-insulator (SOI) integrated circuit and a method of fabricating the SOI integrated circuit are provided. At least one isolated transistor active region and a body line are formed on an SOI substrate. The transistor active region and the body line are surrounded by an isolation layer which is in contact with a buried insulating layer of the SOI substrate. A portion of the sidewall of the transistor active region is extended to the body line. Thus, the transistor active region is electrically connected to the body line through a body extension. The body extension is covered with a body insulating layer. An insulated gate pattern is formed over the transistor active region, and one end of the gate pattern is overlapped with the body insulating layer.

    摘要翻译： 提供了绝缘体上硅（SOI）集成电路和制造SOI集成电路的方法。 在SOI衬底上形成至少一个隔离晶体管有源区和体线。 晶体管有源区和体线被与SOI衬底的掩埋绝缘层接触的隔离层围绕。 晶体管有源区的侧壁的一部分延伸到主体线。 因此，晶体管有源区域通过主体延伸部电连接到主体线路。 身体延伸部分覆盖有身体绝缘层。 绝缘栅图案形成在晶体管有源区上方，栅极图案的一端与主体绝缘层重叠。

    SOI semiconductor integrated circuit for eliminating floating body effects in SOI MOSFETs and method of fabricating the same
    4.
    发明授权
    SOI semiconductor integrated circuit for eliminating floating body effects in SOI MOSFETs and method of fabricating the same 有权
    用于消除SOI MOSFET中的浮体效应的SOI半导体集成电路及其制造方法

    公开(公告)号：US06521959B2

    公开(公告)日：2003-02-18

    申请号：US09782116

    申请日：2001-02-13

    申请人： Young-Wug Kim ,  Byung-Sun Kim ,  Hee-Sung Kang ,  Young-Gun Ko ,  Sung-Dae Park ,  Min-Su Kim ,  Kwang-Il Kim

    发明人： Young-Wug Kim ,  Byung-Sun Kim ,  Hee-Sung Kang ,  Young-Gun Ko ,  Sung-Dae Park ,  Min-Su Kim ,  Kwang-Il Kim

    IPC分类号： H01L2972

    CPC分类号： H01L29/78615

    摘要： A silicon-on-insulator (SOI) integrated circuit and a method of fabricating the SOI integrated circuit are provided. At least one isolated transistor active region and a body line are formed on an SOI substrate. The transistor active region and the body line are surrounded by an isolation layer which is in contact with a buried insulating layer of the SOI substrate. A portion of the sidewall of the transistor active region is extended to the body line. Thus, the transistor active region is electrically connected to the body line through a body extension. The body extension is covered with a body insulating layer. An insulated gate pattern is formed over the transistor active region, and one end of the gate pattern is overlapped with the body insulating layer.

    摘要翻译： 提供了绝缘体上硅（SOI）集成电路和制造SOI集成电路的方法。 在SOI衬底上形成至少一个隔离晶体管有源区和体线。 晶体管有源区和体线被与SOI衬底的掩埋绝缘层接触的隔离层围绕。 晶体管有源区的侧壁的一部分延伸到主体线。 因此，晶体管有源区域通过主体延伸部电连接到主体线路。 身体延伸部分覆盖有身体绝缘层。 绝缘栅图案形成在晶体管有源区上方，栅极图案的一端与主体绝缘层重叠。

    Reduced floating body effect static random access memory cells and methods for fabricating the same
    5.
    发明授权
    Reduced floating body effect static random access memory cells and methods for fabricating the same 失效
    减少浮体效应静态随机存取存储单元及其制造方法

    公开(公告)号：US07105900B2

    公开(公告)日：2006-09-12

    申请号：US10388353

    申请日：2003-03-13

    申请人： Mu-Kyoung Jung ,  Young-Wug Kim ,  Hee-Sung Kang

    发明人： Mu-Kyoung Jung ,  Young-Wug Kim ,  Hee-Sung Kang

    IPC分类号： H01L29/76

    CPC分类号： H01L27/11 ,  H01L21/84 ,  H01L27/1104 ,  H01L27/1203

    摘要： An SRAM cell that may reduce or eliminate floating body effect when using a SOI and a method for fabricating the same are provided. A floating body of an access transistor of the SRAM is connected to a source region of a driver transistor, for example, through a body extension region extending from an active region. A silicide layer may be formed or a ground line contact may be over-etched to form a conductive contact plug that may provide a current path between the body exterior regions and the source region of the driver transistor.

    摘要翻译： 提供了当使用SOI时可以减少或消除浮体效应的SRAM单元及其制造方法。 SRAM的存取晶体管的浮体例如通过从有源区延伸的体延伸区域连接到驱动晶体管的源极区域。 可以形成硅化物层或接地线接触可能被过度蚀刻以形成可在主体外部区域和驱动晶体管的源极区域之间提供电流路径的导电接触插塞。

    CMOS transistor having different PMOS and NMOS gate electrode structures and method of fabrication thereof
    6.
    发明授权
    CMOS transistor having different PMOS and NMOS gate electrode structures and method of fabrication thereof 有权
    CMOS晶体管具有不同的PMOS和NMOS栅电极结构及其制造方法

    公开(公告)号：US07348636B2

    公开(公告)日：2008-03-25

    申请号：US11030245

    申请日：2005-01-06

    申请人： Hyuk-Ju Ryu ,  Young-Wug Kim ,  Chang-Bong Oh ,  Hee-Sung Kang

    发明人： Hyuk-Ju Ryu ,  Young-Wug Kim ,  Chang-Bong Oh ,  Hee-Sung Kang

    IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/00

    CPC分类号： H01L27/092 ,  H01L21/823842

    摘要： In a CMOS semiconductor device using a silicon germanium gate and a method of fabricating the same, a gate insulating layer, a conductive electrode layer that is a seed layer, a silicon germanium electrode layer, and an amorphous conductive electrode layer are sequentially formed on a semiconductor substrate. A photolithographic process is then carried out to remove the silicon germanium electrode layer in the NMOS region, so that the silicon germanium layer is formed only in the PMOS region and is not formed in the NMOS region.

    摘要翻译： 在使用硅锗栅极的CMOS半导体器件及其制造方法中，栅极绝缘层，作为晶种层的导电电极层，硅锗电极层和非晶导电电极层依次形成在 半导体衬底。 然后进行光刻工艺以除去NMOS区域中的硅锗电极层，使得硅锗层仅形成在PMOS区域中，并且不形成在NMOS区域中。

    Methods for fabricating reduced floating body effect static random access memory cells
    8.
    发明授权
    Methods for fabricating reduced floating body effect static random access memory cells 失效
    制造减少浮体效应静态随机存取存储单元的方法

    公开(公告)号：US07410843B2

    公开(公告)日：2008-08-12

    申请号：US11428911

    申请日：2006-07-06

    申请人： Mu-Kyoung Jung ,  Young-Wug Kim ,  Hee-Sung Kang

    发明人： Mu-Kyoung Jung ,  Young-Wug Kim ,  Hee-Sung Kang

    IPC分类号： H01L21/84

    CPC分类号： H01L27/11 ,  H01L21/84 ,  H01L27/1104 ,  H01L27/1203

    摘要： An SRAM cell that may reduce or eliminate floating body effect when using a SOI and a method for fabricating the same are provided. A floating body of an access transistor of the SRAM is connected to a source region of a driver transistor, for example, through a body extension region extending from an active region. A silicide layer may be formed or a ground line contact may be over-etched to form a conductive contact plug that may provide a current path between the body exterior regions and the source region of the driver transistor.

    摘要翻译： 提供了当使用SOI时可以减少或消除浮体效应的SRAM单元及其制造方法。 SRAM的存取晶体管的浮体例如通过从有源区延伸的体延伸区域连接到驱动晶体管的源极区域。 可以形成硅化物层或接地线接触可能被过度蚀刻以形成可在主体外部区域和驱动晶体管的源极区域之间提供电流路径的导电接触插塞。

    Methods for Fabricating Reduced Floating Body Effect Static Random Access Memory Cells
    10.
    发明申请
    Methods for Fabricating Reduced Floating Body Effect Static Random Access Memory Cells 失效
    制造减少浮体效应的方法静态随机存取存储单元

    公开(公告)号：US20060246605A1

    公开(公告)日：2006-11-02

    申请号：US11428911

    申请日：2006-07-06

    申请人： Mu-Kyoung Jung ,  Young-Wug Kim ,  Hee-Sung Kang

    发明人： Mu-Kyoung Jung ,  Young-Wug Kim ,  Hee-Sung Kang

    IPC分类号： H01L21/00

    CPC分类号： H01L27/11 ,  H01L21/84 ,  H01L27/1104 ,  H01L27/1203

    摘要： An SRAM cell that may reduce or eliminate floating body effect when using a SOI and a method for fabricating the same are provided. A floating body of an access transistor of the SRAM is connected to a source region of a driver transistor, for example, through a body extension region extending from an active region. A silicide layer may be formed or a ground line contact may be over-etched to form a conductive contact plug that may provide a current path between the body exterior regions and the source region of the driver transistor.

    摘要翻译： 提供了当使用SOI时可以减少或消除浮体效应的SRAM单元及其制造方法。 SRAM的存取晶体管的浮体例如通过从有源区延伸的体延伸区域连接到驱动晶体管的源极区域。 可以形成硅化物层或接地线接触可能被过度蚀刻以形成可在主体外部区域和驱动晶体管的源极区域之间提供电流路径的导电接触插塞。