公开(公告)号：US06521959B2

公开(公告)日：2003-02-18

申请号：US09782116

申请日：2001-02-13

申请人： Young-Wug Kim ,  Byung-Sun Kim ,  Hee-Sung Kang ,  Young-Gun Ko ,  Sung-Dae Park ,  Min-Su Kim ,  Kwang-Il Kim

发明人： Young-Wug Kim ,  Byung-Sun Kim ,  Hee-Sung Kang ,  Young-Gun Ko ,  Sung-Dae Park ,  Min-Su Kim ,  Kwang-Il Kim

IPC分类号： H01L2972

CPC分类号： H01L29/78615

摘要： A silicon-on-insulator (SOI) integrated circuit and a method of fabricating the SOI integrated circuit are provided. At least one isolated transistor active region and a body line are formed on an SOI substrate. The transistor active region and the body line are surrounded by an isolation layer which is in contact with a buried insulating layer of the SOI substrate. A portion of the sidewall of the transistor active region is extended to the body line. Thus, the transistor active region is electrically connected to the body line through a body extension. The body extension is covered with a body insulating layer. An insulated gate pattern is formed over the transistor active region, and one end of the gate pattern is overlapped with the body insulating layer.

摘要翻译： 提供了绝缘体上硅（SOI）集成电路和制造SOI集成电路的方法。 在SOI衬底上形成至少一个隔离晶体管有源区和体线。 晶体管有源区和体线被与SOI衬底的掩埋绝缘层接触的隔离层围绕。 晶体管有源区的侧壁的一部分延伸到主体线。 因此，晶体管有源区域通过主体延伸部电连接到主体线路。 身体延伸部分覆盖有身体绝缘层。 绝缘栅图案形成在晶体管有源区上方，栅极图案的一端与主体绝缘层重叠。

公开(公告)号：US06703280B2

公开(公告)日：2004-03-09

申请号：US10330404

申请日：2002-12-27

申请人： Young-Wug Kim ,  Byung-Sun Kim ,  Hee-Sung Kang ,  Young-Gun Ko ,  Sung-Bae Park ,  Min-Su Kim ,  Kwang-Il Kim

发明人： Young-Wug Kim ,  Byung-Sun Kim ,  Hee-Sung Kang ,  Young-Gun Ko ,  Sung-Bae Park ,  Min-Su Kim ,  Kwang-Il Kim

IPC分类号： H01L218244

CPC分类号： H01L29/78615

摘要： A silicon-on-insulator (SOI) integrated circuit and a method of fabricating the SOI integrated circuit are provided. At least one isolated transistor active region and a body line are formed on an SOI substrate. The transistor active region and the body line are surrounded by an isolation layer which is in contact with a buried insulating layer of the SOI substrate. A portion of the sidewall of the transistor active region is extended to the body line. Thus, the transistor active region is electrically connected to the body line through a body extension. The body extension is covered with a body insulating layer. An insulated gate pattern is formed over the transistor active region, and one end of the gate pattern is overlapped with the body insulating layer.

摘要翻译： 提供了绝缘体上硅（SOI）集成电路和制造SOI集成电路的方法。 在SOI衬底上形成至少一个隔离晶体管有源区和体线。 晶体管有源区和体线被与SOI衬底的掩埋绝缘层接触的隔离层围绕。 晶体管有源区的侧壁的一部分延伸到主体线。 因此，晶体管有源区域通过主体延伸部电连接到主体线路。 身体延伸部分覆盖有身体绝缘层。 绝缘栅图案形成在晶体管有源区上方，栅极图案的一端与主体绝缘层重叠。

公开(公告)号：US06498370B1

公开(公告)日：2002-12-24

申请号：US09695341

申请日：2000-10-24

申请人： Young-Wug Kim ,  Byung-Sun Kim ,  Hee-Sung Kang ,  Young-Gun Ko ,  Sung-Bae Park

发明人： Young-Wug Kim ,  Byung-Sun Kim ,  Hee-Sung Kang ,  Young-Gun Ko ,  Sung-Bae Park

IPC分类号： H01L2701

CPC分类号： H01L29/78615

摘要： A silicon-on-insulator (SOD integrated circuit and a method of fabricating the SOI integrated circuit are provided. At least one isolated transistor active region and a body line are formed on an SOI substrate. The transistor active region and the body line are surrounded by an isolation layer which is in contact with a buried insulating layer of the SOI substrate. A portion of the sidewall of the transistor active region is extended to the body line. Thus, the transistor active region is electrically connected to the body line through a body extension. The body extension is covered with a body insulating layer. An insulated gate pattern is formed over the transistor active region, and one end of the gate pattern is overlapped with the body insulating layer.

摘要翻译： 提供绝缘体上硅（SOD集成电路和制造SOI集成电路的方法），在SOI衬底上形成至少一个隔离晶体管有源区和体线，晶体管有源区和体线被包围 通过与SOI衬底的埋置绝缘层接触的隔离层，将晶体管有源区的侧壁的一部分延伸到体线，由此，晶体管有源区域通过a 主体延伸部由主体绝缘层覆盖，在晶体管有源区域上形成绝缘栅极图案，栅极图案的一端与主体绝缘层重叠。

公开(公告)号：US06706569B2

公开(公告)日：2004-03-16

申请号：US10285790

申请日：2002-11-01

申请人： Young-Wug Kim ,  Byung-Sun Kim ,  Hee-Sung Kang ,  Young-Gun Ko ,  Sung-Bae Park

发明人： Young-Wug Kim ,  Byung-Sun Kim ,  Hee-Sung Kang ,  Young-Gun Ko ,  Sung-Bae Park

IPC分类号： H01L2100

CPC分类号： H01L29/78615

摘要： A silicon-on-insulator (SOI) integrated circuit and a method of fabricating the SOI integrated circuit are provided. At least one isolated transistor active region and a body line are formed on an SOI substrate. The transistor active region and the body line are surrounded by an isolation layer which is in contact with a buried insulating layer of the SOI substrate. A portion of the sidewall of the transistor active region is extended to the body line. Thus, the transistor active region is electrically connected to the body line through a body extension. The body extension is covered with a body insulating layer. An insulated gate pattern is formed over the transistor active region, and one end of the gate pattern is overlapped with the body insulating layer.

公开(公告)号：US06689648B2

公开(公告)日：2004-02-10

申请号：US10134798

申请日：2002-04-29

申请人： Young-Gun Ko ,  Byung-Sun Kim ,  Young-Wug Kim

发明人： Young-Gun Ko ,  Byung-Sun Kim ,  Young-Wug Kim

IPC分类号： H01L2100

CPC分类号： H01L27/1203 ,  H01L21/84

摘要： The present invention relates to an SOI semiconductor device and a method for fabricating an SOI semiconductor device, in which the portions formed with silicide layers are laterally restricted by spacers to a predetermined range in the diffusion regions to be used for diodes or well resistors. In this manner, it is possible to fix the length of distance between the sides of a silicide layer and a diffusion region, greater than that available in the prior art techniques, thereby minimizing power leakage at the sides of the diffusion regions. In the SOI semiconductor device thus constructed, the diffusion regions to be used for diodes (or well resistors) are constructed with spacers in a double junction structure of different density of impurity layers (for instance, a P− or N− layer respectively surrounds a P+ or N+ layer), in other words, only onto a high density of impurity layer, the P+ or N+ layer, or in a single junction structure in which the spacers restrict a range of space for forming the silicide layer in the diffusion region.

摘要翻译： SOI半导体器件及SOI半导体器件的制造方法本发明涉及一种SOI半导体器件的制造方法，其中由硅化物层形成的部分在隔离层中被横向限制在用于二极管或阱电阻器的扩散区域中的预定范围内。 以这种方式，可以固定硅化物层和扩散区域的侧面之间的距离长度，大于现有技术中可用的距离，从而最小化扩散区域侧面的功率泄漏。 在如此构造的SOI半导体器件中，用于二极管（或阱电阻器）的扩散区域由具有不同密度杂质层的双结结构中的间隔物构成（例如，P-或N-层分别围绕 P +或N +层），换句话说，仅在高密度的杂​​质层，P +或N +层上，或在单结结构中，其中间隔物限制在扩散区域中形成硅化物层的空间范围。

公开(公告)号：US06407429B1

公开(公告)日：2002-06-18

申请号：US09658099

申请日：2000-09-08

申请人： Young-Gun Ko ,  Byung-Sun Kim ,  Young-Wug Kim

发明人： Young-Gun Ko ,  Byung-Sun Kim ,  Young-Wug Kim

IPC分类号： H01L310392

CPC分类号： H01L27/1203 ,  H01L21/84

摘要： The present invention relates to an SOI semiconductor device and a method for fabricating an SOI semiconductor device, in which the portions formed with silicide layers are laterally restricted by spacers to a predetermined range in the diffusion regions to be used for diodes or well resistors. In this manner, it is possible to fix the length of distance between the sides of a silicide layer and a diffusion region, greater than that available in the prior art techniques, thereby minimizing power leakage at the sides of the diffusion regions. In the SOI semiconductor device thus constructed, the diffusion regions to be used for diodes (or well resistors) are constructed with spacers in a double junction structure of different density of impurity layers (for instance, a P− or N− layer respectively surrounds a P+ or N+ layer), in other words, only onto a high density of impurity layer, the P+ or N+ layer, or in a single junction structure in which the spacers restrict a range of space for forming the silicide layer in the diffusion region.

公开(公告)号：US06693325B1

公开(公告)日：2004-02-17

申请号：US09640851

申请日：2000-08-17

申请人： Young-Gun Ko ,  Byung-Sun Kim

发明人： Young-Gun Ko ,  Byung-Sun Kim

IPC分类号： H01L2712

CPC分类号： H01L21/76264 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203

摘要： The present invention relates to a highly integrated SOI semiconductor device and a method for fabricating the SOI semiconductor device by reducing a distance between diodes or well resistors without any reduction in insulating characteristics. The device includes a first conductivity type semiconductor substrate and a surface silicon layer formed by inserting an insulating layer on the semiconductor substrate. A trench is formed by etching a predetermined portion of surface silicon layer, insulating layer and substrate to expose a part of the semiconductor substrate to be used for an element separating region, and a STI is formed in the trench. A transistor is constructed on the surface silicon layer surrounded by the insulating layer and STI with a gate electrode being positioned at the center thereof and with source/drain region being formed in the surface silicon layer of both edges of the gate electrode for enabling its bottom part to be in contact with the insulating layer. A first groove is formed between the STI at one side of the transistor by etching the surface silicon layer and insulating layer to expose a predetermined portion of an active region of a second conductivity type well in the semiconductor substrate. A second groove is formed between the STI at one side of the first groove by etching the surface silicon layer and insulating layer to expose a predetermined portion of the active region of the semiconductor substrate. A first diode diffusion region of a first conductivity type is formed in a second conductivity type well under the first groove, and a second diode diffusion region of a second conductivity type is formed in the semiconductor substrate under the second groove.

摘要翻译： 本发明涉及一种高度集成的SOI半导体器件以及通过减小二极管或阱电阻之间的距离而不会降低绝缘特性来制造SOI半导体器件的方法。 该器件包括第一导电型半导体衬底和通过在半导体衬底上插入绝缘层而形成的表面硅层。 通过蚀刻表面硅层，绝缘层和衬底的预定部分以暴露用于元件分离区域的半导体衬底的一部分而形成沟槽，并且在沟槽中形成STI。 晶体管构造在被绝缘层包围的表面硅层上，STI与栅电极位于其中心，源/漏区形成在栅电极的两个边缘的表面硅层中，以使其底部 部分与绝缘层接触。 通过蚀刻表面硅层和绝缘层，在晶体管的一侧的STI之间形成第一凹槽，以暴露半导体衬底中阱的第二导电类型的有源区的预定部分。 通过蚀刻表面硅层和绝缘层，在第一凹槽的一侧的STI之间形成第二凹槽，以露出半导体衬底的有源区的预定部分。 第一导电类型的第一二极管扩散区形成在第一沟槽下面的第二导电类型阱中，并且在第二沟槽下面的半导体衬底中形成第二导电类型的第二二极管扩散区。

公开(公告)号：US06844223B2

公开(公告)日：2005-01-18

申请号：US10738724

申请日：2003-12-17

申请人： Young-Gun Ko ,  Byung-Sun Kim

发明人： Young-Gun Ko ,  Byung-Sun Kim

IPC分类号： H01L27/08 ,  H01L21/20 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/00 ,  H01L27/06 ,  H01L27/12 ,  H01L21/00

CPC分类号： H01L21/76264 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203

摘要： The present invention relates to a highly integrated SOI semiconductor device and a method for fabricating the SOI semiconductor device by reducing a distance between diodes or well resistors without any reduction in insulating characteristics. The device includes a first conductivity type semiconductor substrate and a surface silicon layer formed by inserting an insulating layer on the semiconductor substrate. A trench is formed by etching a predetermined portion of surface silicon layer, insulating layer and substrate to expose a part of the semiconductor substrate to be used for an element separating region, and a STI is formed in the trench. A transistor is constructed on the surface silicon layer surrounded by the insulating layer and STI with a gate electrode being positioned at the center thereof and with source/drain region being formed in the surface silicon layer of both edges of the gate electrode for enabling its bottom part to be in contact with the insulating layer. A first groove is formed between the STI at one side of the transistor by etching the surface silicon layer and insulating layer to expose a predetermined portion of an active region of a second conductivity type well in the semiconductor substrate. A second groove is formed between the STI at one side of the first groove by etching the surface silicon layer and insulating layer to expose a predetermined portion of the active region of the semiconductor substrate. A first diode diffusion region of a first conductivity type is formed in a second conductivity type well under the first groove, and a second diode diffusion region of a second conductivity type is formed in the semiconductor substrate under the second groove.

摘要翻译： 本发明涉及一种高度集成的SOI半导体器件以及通过减小二极管或阱电阻之间的距离而不会降低绝缘特性来制造SOI半导体器件的方法。 该器件包括第一导电型半导体衬底和通过在半导体衬底上插入绝缘层而形成的表面硅层。 通过蚀刻表面硅层，绝缘层和衬底的预定部分以暴露用于元件分离区域的半导体衬底的一部分而形成沟槽，并且在沟槽中形成STI。 晶体管构造在被绝缘层包围的表面硅层上，STI与栅电极位于其中心，源/漏区形成在栅电极的两个边缘的表面硅层中，以使其底部 部分与绝缘层接触。 通过蚀刻表面硅层和绝缘层，在晶体管的一侧的STI之间形成第一凹槽，以暴露半导体衬底中阱的第二导电类型的有源区的预定部分。 通过蚀刻表面硅层和绝缘层，在第一凹槽的一侧的STI之间形成第二凹槽，以露出半导体衬底的有源区的预定部分。 第一导电类型的第一二极管扩散区形成在第一沟槽下面的第二导电类型阱中，并且在第二沟槽下面的半导体衬底中形成第二导电类型的第二二极管扩散区。

公开(公告)号：US08962435B2

公开(公告)日：2015-02-24

申请号：US14508250

申请日：2014-10-07

申请人： Shigenobu Maeda ,  Hidenobu Fukutome ,  Young-Gun Ko ,  Joo-Hyun Jeong

发明人： Shigenobu Maeda ,  Hidenobu Fukutome ,  Young-Gun Ko ,  Joo-Hyun Jeong

IPC分类号： H01L21/336 ,  H01L29/66 ,  H01L21/02

CPC分类号： H01L29/7842 ,  H01L21/02532 ,  H01L21/02587 ,  H01L21/02636 ,  H01L21/02658 ,  H01L29/045 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

摘要： A semiconductor device can include an active region having a fin portion providing a channel region between opposing source and drain regions. A gate electrode can cross over the channel region between the opposing source and drain regions and first and second strain inducing structures can be on opposing sides of the gate electrode and can be configured to induce strain on the channel region, where each of the first and second strain inducing structures including a respective facing side having a pair of {111} crystallographically oriented facets.

摘要翻译： 半导体器件可以包括有源区，其具有提供相对的源极和漏极区之间的沟道区的鳍部。 栅电极可以跨越在相对的源极和漏极区域之间的沟道区域上，并且第一和第二应变诱导结构可以在栅电极的相对侧上，并且可以被配置为在沟道区域上引起应变，其中第一和 第二应变诱导结构，其包括具有一对{111}晶体取向小面的相应的相对侧。

公开(公告)号：US09240481B2

公开(公告)日：2016-01-19

申请号：US14596291

申请日：2015-01-14

申请人： Shigenobu Maeda ,  Hidenobu Fukutome ,  Young-Gun Ko ,  Joo-Hyun Jeong

发明人： Shigenobu Maeda ,  Hidenobu Fukutome ,  Young-Gun Ko ,  Joo-Hyun Jeong

IPC分类号： H01L29/10 ,  H01L29/78 ,  H01L29/04 ,  H01L21/02 ,  H01L29/66

CPC分类号： H01L29/7842 ,  H01L21/02532 ,  H01L21/02587 ,  H01L21/02636 ,  H01L21/02658 ,  H01L29/045 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

摘要： A semiconductor device can include an active region having a fin portion providing a channel region between opposing source and drain regions. A gate electrode can cross over the channel region between the opposing source and drain regions and first and second strain inducing structures can be on opposing sides of the gate electrode and can be configured to induce strain on the channel region, where each of the first and second strain inducing structures including a respective facing side having a pair of {111} crystallographically oriented facets.

摘要翻译： 半导体器件可以包括有源区，其具有提供相对的源极和漏极区之间的沟道区的鳍部。 栅电极可以跨越在相对的源极和漏极区域之间的沟道区域上，并且第一和第二应变诱导结构可以在栅电极的相对侧上，并且可以被配置为在沟道区域上引起应变，其中第一和 第二应变诱导结构，其包括具有一对{111}晶体取向小面的相应的相对侧。