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公开(公告)号：US07962864B2
公开(公告)日：2011-06-14
申请号：US12154458
申请日：2008-05-22
CPC分类号： G06F17/5068 , G06F2217/10
摘要： In one embodiment, a method for predicting yield during the design stage includes receiving defectivity data identifying defects associated with previous wafer designs, and dividing the defects into systematic defects and random defects. For each design layout of a new wafer design, yield is predicted separately for the systematic defects and the random defects. A combined yield is then calculated based on the yield predicted for the systematic defects and the yield predicted for the random defects.
摘要翻译： 在一个实施例中，用于在设计阶段预测产量的方法包括接收识别与先前晶片设计相关的缺陷的缺陷率数据，以及将缺陷划分为系统缺陷和随机缺陷。 对于新的晶片设计的每个设计布局，对于系统缺陷和随机缺陷分别预测产量。 然后根据系统缺陷预测的产量和随机缺陷预测的产量计算组合产量。
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公开(公告)号：US20080295047A1
公开(公告)日：2008-11-27
申请号：US12154458
申请日：2008-05-22
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/10
摘要： In one embodiment, a method for predicting yield during the design stage includes receiving defectivity data identifying defects associated with previous wafer designs, and dividing the defects into systematic defects and random defects. For each design layout of a new wafer design, yield is predicted separately for the systematic defects and the random defects. A combined yield is then calculated based on the yield predicted for the systematic defects and the yield predicted for the random defects.
摘要翻译： 在一个实施例中，用于在设计阶段预测产量的方法包括接收识别与先前晶片设计相关的缺陷的缺陷率数据，以及将缺陷划分为系统缺陷和随机缺陷。 对于新的晶片设计的每个设计布局，对于系统缺陷和随机缺陷分别预测产量。 然后根据系统缺陷预测的产量和随机缺陷预测的产量计算组合产量。
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公开(公告)号：US20080294281A1
公开(公告)日：2008-11-27
申请号：US12154459
申请日：2008-05-22
CPC分类号： G06F17/504 , G05B19/41875 , G05B2219/32222 , G06F2217/10 , G06Q10/04 , G06Q50/04 , Y02P90/22 , Y02P90/30
摘要： In one embodiment, a method for predicting yield includes calculating a criticality factor (CF) for each of a plurality of defects detected in an inspection process step of a wafer, and determining a yield-loss contribution of the inspection process step to the final yield based on CFs of the plurality of defects and the yield model built for a relevant design. The yield-loss contribution of the inspection process step is then used to predict the final yield for the wafer.
摘要翻译： 在一个实施例中，用于预测产量的方法包括计算在晶片的检查处理步骤中检测到的多个缺陷中的每个缺陷因子（CF），并且将检查处理步骤的屈服损失贡献确定为最终产量 基于多个缺陷的CFs和为相关设计构建的收益模型。 然后使用检查处理步骤的屈服损失贡献来预测晶片的最终产量。
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公开(公告)号：US20080295048A1
公开(公告)日：2008-11-27
申请号：US12154629
申请日：2008-05-22
IPC分类号： G06F17/50
CPC分类号： G01R31/318511
摘要： In one embodiment, an inline defect analysis method includes receiving geometric characteristics of individual defects and design data corresponding to the individual defects, determining which of the individual defects are likely to be nuisance defects using the geometric characteristics and the corresponding design data, and refraining from sampling the defects that are likely to be nuisance defects.
摘要翻译： 在一个实施例中，内联缺陷分析方法包括接收单个缺陷的几何特征和对应于各个缺陷的设计数据，使用几何特征和对应的设计数据确定哪些单个缺陷可能是滋扰缺陷，并且避免 对可能是滋扰缺陷的缺陷进行抽样。
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公开(公告)号：US08799831B2
公开(公告)日：2014-08-05
申请号：US12154629
申请日：2008-05-22
IPC分类号： G06F17/50
CPC分类号： G01R31/318511
摘要： In one embodiment, an inline defect analysis method includes receiving geometric characteristics of individual defects and design data corresponding to the individual defects, determining which of the individual defects are likely to be nuisance defects using the geometric characteristics and the corresponding design data, and refraining from sampling the defects that are likely to be nuisance defects.
摘要翻译： 在一个实施例中，内联缺陷分析方法包括接收单个缺陷的几何特征和对应于各个缺陷的设计数据，使用几何特征和对应的设计数据确定哪些单个缺陷可能是滋扰缺陷，并且避免 对可能是滋扰缺陷的缺陷进行抽样。
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6.发明授权Dynamic inline yield analysis and prediction of a defect limited yield using inline inspection defects 有权使用在线检测缺陷的动态在线产量分析和预测缺陷限制产量公开(公告)号：US07937179B2
公开(公告)日：2011-05-03
申请号：US12154459
申请日：2008-05-22
CPC分类号： G06F17/504 , G05B19/41875 , G05B2219/32222 , G06F2217/10 , G06Q10/04 , G06Q50/04 , Y02P90/22 , Y02P90/30
摘要： In one embodiment, a method for predicting yield includes calculating a criticality factor (CF) for each of a plurality of defects detected in an inspection process step of a wafer, and determining a yield-loss contribution of the inspection process step to the final yield based on CFs of the plurality of defects and the yield model built for a relevant design. The yield-loss contribution of the inspection process step is then used to predict the final yield for the wafer.
摘要翻译： 在一个实施例中，用于预测产量的方法包括计算在晶片的检查处理步骤中检测到的多个缺陷中的每个缺陷因子（CF），并且将检查处理步骤的屈服损失贡献确定为最终产量 基于多个缺陷的CFs和为相关设计构建的收益模型。 然后使用检查处理步骤的屈服损失贡献来预测晶片的最终产量。
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7.发明申请Method and apparatus for determining factors for design consideration in yield analysis 有权用于确定产量分析中设计考虑因素的方法和装置公开(公告)号：US20080295063A1
公开(公告)日：2008-11-27
申请号：US12154586
申请日：2008-05-22
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F2217/10
摘要： Embodiments of the present invention provide methods and apparatuses for determining factors for design consideration in yield analysis of semiconductor fabrication. In one embodiment, a computer-implemented method for determining factors for design consideration in yield analysis of semiconductor fabrication includes obtaining a geometric characteristic of a defect on a chip and obtaining design data of the chip, where the design data is associated with the defect. The method further includes determining a criticality factor of the defect based on the geometric characteristic and the design data, and outputting the criticality factor.
摘要翻译： 本发明的实施例提供了用于确定半导体制造的成品率分析中的设计考虑因素的方法和装置。 在一个实施例中，用于确定半导体制造的成品率分析中的设计考虑因素的计算机实现方法包括获得芯片上的缺陷的几何特性并获得设计数据与缺陷相关联的芯片的设计数据。 该方法还包括基于几何特征和设计数据确定缺陷的关键因素，并输出关键因素。
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8.发明授权Method and apparatus for determining factors for design consideration in yield analysis 有权用于确定产量分析中设计考虑因素的方法和装置公开(公告)号：US08924904B2
公开(公告)日：2014-12-30
申请号：US12154586
申请日：2008-05-22
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F2217/10
摘要： Embodiments of the present invention provide methods and apparatuses for determining factors for design consideration in yield analysis of semiconductor fabrication. In one embodiment, a computer-implemented method for determining factors for design consideration in yield analysis of semiconductor fabrication includes obtaining a geometric characteristic of a defect on a chip and obtaining design data of the chip, where the design data is associated with the defect. The method further includes determining a criticality factor of the defect based on the geometric characteristic and the design data, and outputting the criticality factor.
摘要翻译： 本发明的实施例提供了用于确定半导体制造的成品率分析中的设计考虑因素的方法和装置。 在一个实施例中，用于确定半导体制造的成品率分析中的设计考虑因素的计算机实现方法包括获得芯片上的缺陷的几何特性并获得设计数据与缺陷相关联的芯片的设计数据。 该方法还包括基于几何特征和设计数据确定缺陷的关键因素，并输出关键因素。
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公开(公告)号：US20070052963A1
公开(公告)日：2007-03-08
申请号：US11553745
申请日：2006-10-27
申请人： JACOB ORBON , Youval Nehmadi , Ofer Bokobza , Ariel Ben-Porath , Erez Ravid , Rinat Shimshi , Vicky Svidenko
发明人： JACOB ORBON , Youval Nehmadi , Ofer Bokobza , Ariel Ben-Porath , Erez Ravid , Rinat Shimshi , Vicky Svidenko
IPC分类号： G01N21/84
CPC分类号： G03F7/7065 , G03F1/84
摘要： Methods and apparatus for categorizing defects on workpieces, such as semiconductor wafers and masks used in lithographically writing patterns into such wafers are provided. For some embodiments, by analyzing the layout in the neighborhood of the defect, and matching it to similar defected neighborhoods in different locations across the die, defects may be categorized by common structures in which they occur.
摘要翻译： 提供了用于将工件上的缺陷（例如半导体晶片和用于将这种晶片刻画图案所用的掩模）分类的方法和装置。 对于一些实施例，通过分析缺陷附近的布局，并且将其匹配到跨越裸片的不同位置中的类似的缺陷邻域，可以通过它们出现的共同结构对缺陷进行分类。
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公开(公告)号：US07760929B2
公开(公告)日：2010-07-20
申请号：US11553745
申请日：2006-10-27
申请人： Jacob J. Orbon , Youval Nehmadi , Ofer Bokobza , Ariel Ben-Porath , Erez Ravid , Rinat Shimshi , Vicky Svidenko
发明人： Jacob J. Orbon , Youval Nehmadi , Ofer Bokobza , Ariel Ben-Porath , Erez Ravid , Rinat Shimshi , Vicky Svidenko
IPC分类号： G06K9/00
CPC分类号： G03F7/7065 , G03F1/84
摘要： Methods and apparatus for categorizing defects on workpieces, such as semiconductor wafers and masks used in lithographically writing patterns into such wafers are provided. For some embodiments, by analyzing the layout in the neighborhood of the defect, and matching it to similar defected neighborhoods in different locations across the die, defects may be categorized by common structures in which they occur.
摘要翻译： 提供了用于将工件上的缺陷（例如半导体晶片和用于将这种晶片刻画图案所用的掩模）分类的方法和装置。 对于一些实施例，通过分析缺陷附近的布局，并且将其匹配到跨越裸片的不同位置中的类似的缺陷邻域，可以通过它们出现的共同结构对缺陷进行分类。
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