摘要:
A converter (311) converts an AC electric power (e) to the DC electric power with a DC voltage value corresponding to a setting. An inverter (312) is controlled by a frequency electric power control circuit (330) to convert the DC electric power to a dual frequency AC electric power for alternately outputting low and high frequencies at a frequency ratio (duty) corresponding to the setting. A matching transformer (321) having a tap (321C) at which the resonance impedance corresponds to the output impedance of a generator (310) receives the dual frequency AC electric power. A low-frequency series resonance circuit (325) or a high-frequency series resonance circuit (326) is caused to provide a series resonance, thereby causing an induction heating coil (200) to induction heat a workpiece-to-be-heated (201). In this way, the single generator (310) and the single induction heating coil (200) are used to effectively induction heat the workpiece-to-be-heated (201) by means of the dual frequency resonance.
摘要:
A converter (311) converts an AC electric power (e) to the DC electric power with a DC voltage value corresponding to a setting. An inverter (312) is controlled by a frequency electric power control circuit (330) to convert the DC electric power to a dual frequency AC electric power for alternately outputting low and high frequencies at a frequency ratio (duty) corresponding to the setting. A matching transformer (321) having a tap (321C) at which the resonance impedance corresponds to the output impedance of a generator (310) receives the dual frequency AC electric power. A low-frequency series resonance circuit (325) or a high-frequency series resonance circuit (326) is caused to provide a series resonance, thereby causing an induction heating coil (200) to induction heat a workpiece-to-be-heated (201). In this way, the single generator (310) and the single induction heating coil (200) are used to effectively induction heat the workpiece-to-be-heated (201) by means of the dual frequency resonance.
摘要:
An induction hardening monitoring apparatus (20) comprising: a current sensor (21) for detecting output current from a high-frequency inverter (11); a voltage sensor for detecting a voltage generated in a heating coil (14) connected between output terminals of the high-frequency inverters (11) together with a capacitor (12) in an equivalent circuit manner; and a controller (23) for monitoring a hardening processing based on a detection signal from the current sensor (21) and a detection signal from a voltage sensor (22), wherein the controller (23) monitors a hardening processing by calculating an effective value of output current from the high-frequency inverter (11) based on a detection signal from the current sensor (21) and calculating an effective value of voltage generated in a heating coil (14) based on a detection signal from the voltage sensor (22); or further calculating load impedance based on each effective value.
摘要:
An induction hardening monitoring apparatus (20) comprising: a current sensor (21) for detecting output current from a high-frequency inverter (11); a voltage sensor for detecting a voltage generated in a heating coil (14) connected between output terminals of the high-frequency inverters (11) together with a capacitor (12) in an equivalent circuit manner; and a controller (23) for monitoring a hardening processing based on a detection signal from the current sensor (21) and a detection signal from a voltage sensor (22), wherein the controller (23) monitors a hardening processing by calculating an effective value of output current from the high-frequency inverter (11) based on a detection signal from the current sensor (21) and calculating an effective value of voltage generated in a heating coil (14) based on a detection signal from the voltage sensor (22); or further calculating load impedance based on each effective value.
摘要:
The present invention includes: a hardening control unit (70) for controlling an induction hardening apparatus (10, 10A) based on setup conditions data regarding the induction hardening apparatus (10, 10A); a hardening monitoring unit (20) that measures, as measurement data, the electric quantity in an electric circuit configured to include a high-frequency inverter (11), a capacitor (12), and a heating coil (14, 14A, 14B) and that monitors an induction hardening status; and a data collecting unit (80) that collects the data from various sensors in the induction hardening apparatus (10, 10A, 10B) obtained when the induction hardening apparatus (10) subjects the work (15, 15A, 15B) to an induction hardening based on the setup conditions data outputted from the hardening control unit (70) and that collects the measurement data from the hardening monitoring unit (20) to store the collected data from the various sensors and the measurement data so that the collected data from the various sensors and the measurement data are associated to each other.
摘要:
Apparatuses and methods for managing jitter resulting from processing through a network interface pipeline are disclosed. In embodiments, a network traffic scheduler annotates packets to be transmitted over a bandwidth-limited network connection with time relationship information to ensure downstream bandwidth limitations are not violated. Following processing through a network interface pipeline, a jitter shaper inspects the annotated time relationship information and pipeline-imposed delays and, by imposing a variable delay, reestablishes bandwidth-complaint time relationships based upon the annotated time relationship information and configured tolerances.
摘要:
A mixed-mode signal detection apparatus suitable for ISO/IEC 14443 Type A and Type B RFID proximity card applications. The apparatus combines switched capacitor sampling and digital post processing to recover information from Amplitude Shift Keying (ASK) modulated signals. A phase detector triggers a pulse generator, which is used to signal sample and hold units that store the peak value of each carrier signal cycle. The samples are used to form a discrete version of the modulation signal and are post-processed digitally to recover encoded signal information.
摘要:
Integrated circuit mask layouts are modified for the purpose of migration to abide a new set of design rules, or for the purpose of optimization for timing, power, signal integrity and manufacturability, among other purposes. The modified layout is required to satisfy a set of constraints generated from design rules, electrical specifications, user specifications among other requirements. The present invention provides a system and a method of representing constraint sets, each of which consists of two or more sets of constraints that are mutually exclusive to each other. In the preferred embodiment, one method of formulation is presented, and a method of solving the layout modification problem under the constraint sets is presented.
摘要:
Mechanisms for analyzing computer instructions implementing a program in which typestate analysis is informed by concurrency analysis. The concurrency-guided typestate analysis may simulate the “worst case” scenario due to thread interleaving by transitioning a simulated state of the variable to a special state whenever the variable is not guarded by its intended guarding lock. While in the special state, the analysis may assume that the state of the simulated variable is the worst possible state with respect to processing operations that may lead to an error depending on the state of the variable. Thus, the analysis performed may assume that referencing the variable in a state-dependent operation while the simulated state of the variable is in the special state may lead to an error, and the analysis may generate a warning, accordingly. The analysis may process the computer instructions to infer which lock is intended to guard a shared variable.
摘要:
In various implementations of the invention, a model of an optical proximity correction process is employed to determine potential adjustments to a layout design for a mask that might resolve potential errors an image resulting from application of the mask in an optical lithographic process. In various implementations of the invention, corrected mask shapes, such as for example optical proximity corrected mask shapes, and associated printed image contours are generated through use of a model. Subsequently, the associated printed image contour and a desired printed image contour may be used to determine various edge segment adjustments to the corrected mask shapes that would realize the desired printed image contour. In various implementations of the present invention, the model for generation of the corrected mask shapes and the associated printed image contour is a square kernel model. With various implementations of the invention, the kernel represents a grey scale map wherein each pixel of the map is generated based on the desired displacement relative to the displacement to be modeled. For example by application of linear regression techniques. As a result, printed image contours and corrected mask shapes may be generated based upon an input layout design, wherein potential adjustments to the mask may be determined based upon a desired printed image contour.