公开(公告)号：US20120056682A1

公开(公告)日：2012-03-08

申请号：US13294086

申请日：2011-11-10

申请人： Yuji SATOH ,  Mototsugu HAMADA ,  Daisuke MIYASHITA

发明人： Yuji SATOH ,  Mototsugu HAMADA ,  Daisuke MIYASHITA

IPC分类号： H03L7/00

CPC分类号： H03L1/026 ,  H03L1/025 ,  H03L7/099 ,  H03L7/0995 ,  H03L2207/06

摘要： A semiconductor integrated circuit device includes a DCO and a storing unit that stores a temperature coefficient of an oscillation frequency and an absolute value of the oscillation frequency, which should be set in the DCO, corresponding to potential obtained from a voltage source that changes with a monotonic characteristic with respect to temperature.

摘要翻译： 半导体集成电路器件包括DCO和存储单元，该存储单元存储在DCO中设置的振荡频率的温度系数和振荡频率的绝对值，对应于从电压源变化的电位获得的电位 关于温度的单调特性。

公开(公告)号：US20110181367A1

公开(公告)日：2011-07-28

申请号：US12726323

申请日：2010-03-17

申请人： Yuji SATOH ,  Mototsugu HAMADA ,  Daisuke MIYASHITA

发明人： Yuji SATOH ,  Mototsugu HAMADA ,  Daisuke MIYASHITA

IPC分类号： H03L7/00

CPC分类号： H03L1/026 ,  H03L1/025 ,  H03L7/099 ,  H03L7/0995 ,  H03L2207/06

摘要： A semiconductor integrated circuit device includes a DCO and a storing unit that stores a temperature coefficient of an oscillation frequency and an absolute value of the oscillation frequency, which should be set in the DCO, corresponding to potential obtained from a voltage source that changes with a monotonic characteristic with respect to temperature.

摘要翻译： 半导体集成电路器件包括DCO和存储单元，该存储单元存储在DCO中设置的振荡频率的温度系数和振荡频率的绝对值，对应于从电压源变化的电位获得的电位 关于温度的单调特性。

公开(公告)号：US20120135700A1

公开(公告)日：2012-05-31

申请号：US13369536

申请日：2012-02-09

申请人： Shouhei KOUSAI ,  Daisuke MIYASHITA ,  Jun DEGUCHI

发明人： Shouhei KOUSAI ,  Daisuke MIYASHITA ,  Jun DEGUCHI

IPC分类号： H04B1/16 ,  H03K5/04

CPC分类号： H03D7/125

摘要： A frequency converting circuit that outputs an output signal obtained by mixing a first input signal and a second input signal, has: a first input terminal to which the first input signal is input; a second input terminal to which the second input signal is input; an output terminal from which the output signal is output; a frequency converting element that has a first input part connected to the first input terminal and an output part connected to the output terminal, restricts the signal input to the first input part according to a signal input to a second input part and outputs the restricted signal to the output part; and a pulse controlling circuit that receives the second input signal via the second input terminal and outputs a pulse signal obtained by restricting the pulses of the second input signal to the second input part of the frequency converting element.

摘要翻译： 输出通过混合第一输入信号和第二输入信号而获得的输出信号的频率转换电路具有：输入第一输入信号的第一输入端; 输入第二输入信号的第二输入端; 输出信号输出的输出端子; 具有连接到第一输入端子的第一输入部分和连接到输出端子的输出部分的频率转换元件根据输入到第二输入部分的信号来限制输入到第一输入部分的信号，并输出受限信号 到输出部分; 以及脉冲控制电路，其经由所述第二输入端子接收所述第二输入信号，并将通过将所述第二输入信号的脉冲限制到所述频率转换元件的所述第二输入部分而获得的脉冲信号。

公开(公告)号：US20130254632A1

公开(公告)日：2013-09-26

申请号：US13601186

申请日：2012-08-31

申请人： Daisuke MIYASHITA

发明人： Daisuke MIYASHITA

IPC分类号： H03M13/13

CPC分类号： G06F11/1008 ,  H03M5/08 ,  H03M13/1117 ,  H03M13/6502 ,  H03M13/6577

摘要： A decoding device is provided for decoding received data which is coded based on low-density parity-check code. The decoding device includes a variable node operation unit, a check node operation unit, and a circuit in the transmission path between the two units. The variable node operation unit generates secondary probability information based on primary probability information and the coded data. The check node operation unit generates the primary probability information based on the secondary probability information. The circuit transmits the primary probability information and the secondary probability information between the variable node operation unit and the check node operation unit. In addition, at least one of the primary probability information and the secondary probability information transmitted via the transmission path is represented by a time signal.

摘要翻译： 提供了一种解码装置，用于对基于低密度奇偶校验码进行编码的接收数据进行解码。 解码装置包括可变节点操作单元，校验节点操作单元和两个单元之间的传输路径中的电路。 可变节点操作单元基于主概率信息和编码数据生成二次概率信息。 校验节点操作单元基于次要概率信息生成主概率信息。 电路在可变节点运算单元和校验节点运算单元之间传输主要概率信息和次要概率信息。 此外，经由传输路径发送的主要概率信息和次要概率信息中的至少一个由时间信号表示。

公开(公告)号：US20100033259A1

公开(公告)日：2010-02-11

申请号：US12500864

申请日：2009-07-10

申请人： Daisuke MIYASHITA

发明人： Daisuke MIYASHITA

IPC分类号： H03B5/12

CPC分类号： H03B5/1228 ,  H03B5/1215 ,  H03B5/1225 ,  H03B5/1243 ,  H03B5/1265

摘要： A semiconductor integrated circuit device includes a plurality of first gates each of which has a first protrusion section protruding from a first active region; a plurality of second gates each of which has a second protrusion section protruding from a second active region adjacent to the first active region in a direction opposite to a protruding direction of the first protrusion section; a second common interconnect which is formed on the first protrusion section of the plurality of first gates and on all drains of the second active region and connects the plurality of first gates and all drains of the second active region; and a third common interconnect which is formed on the second protrusion section of the plurality of second gates and on all drains of the first active region and connects the plurality of second gates and all drains of the first active region.

摘要翻译： 半导体集成电路器件包括多个第一栅极，每个栅极具有从第一有源区域突出的第一突出部分; 多个第二栅极，其具有从与所述第一有源区域相邻的第二有源区域沿与所述第一突出部的突出方向相反的方向突出的第二突出部; 第二公共互连，其形成在所述多个第一栅极的所述第一突出部分和所述第二有源区域的所有漏极上，并且连接所述多个第一栅极和所述第二有源区域的所有漏极; 以及第三公共互连，其形成在所述多个第二栅极的第二突出部分和所述第一有源区域的所有漏极上，并且连接所述多个第二栅极和所述第一有源区域的所有漏极。

公开(公告)号：US20090289732A1

公开(公告)日：2009-11-26

申请号：US12434807

申请日：2009-05-04

申请人： Daisuke MIYASHITA

发明人： Daisuke MIYASHITA

IPC分类号： H03B5/18

CPC分类号： H03B5/1228 ,  H03B5/1215 ,  H03B5/1225 ,  H03B5/1243 ,  H03B5/1265 ,  H03B2200/0046 ,  H03B2200/0048 ,  H03B2200/005 ,  H03B2201/031

摘要： A semiconductor integrated circuit includes: a resonance circuit configured to determine an oscillation frequency; a first MOS transistor connected to the resonance circuit and configured to constitute an oscillation unit for delivering an oscillation output having the oscillation frequency; a second MOS transistor connected in parallel with the first MOS transistor; and a control unit configured to turn on and off the second MOS transistor according to the oscillation frequency, thereby enabling an equivalent gate width based on the first and second MOS transistors to be increased and decreased. Consequently, there is obtained an oscillation output having reduced phase noise, while an adequate oscillation margin is maintained.

摘要翻译： 半导体集成电路包括：谐振电路，被配置为确定振荡频率; 连接到谐振电路的第一MOS晶体管，其构成为构成用于输送具有振荡频率的振荡输出的振荡单元; 与第一MOS晶体管并联连接的第二MOS晶体管; 以及控制单元，被配置为根据振荡频率接通和断开第二MOS晶体管，从而能够增加和减少基于第一和第二MOS晶体管的等效栅极宽度。 因此，获得具有相位噪声降低的振荡输出，同时保持足够的振荡余量。

公开(公告)号：US20100237956A1

公开(公告)日：2010-09-23

申请号：US12555985

申请日：2009-09-09

申请人： Daisuke MIYASHITA

发明人： Daisuke MIYASHITA

IPC分类号： H03B5/12 ,  G05F1/10

CPC分类号： H03B5/1228 ,  H03B5/1215 ,  H03B5/1243 ,  H03B5/1278

摘要： This invention includes a bias origination section configured to originate an original bias voltage; a comparison section configured to compare the original bias voltage and a comparison voltage, and output a comparison result; a resistive divider section composed by a resistance circuit including a variable resistor section having a resistor and a switch, and configured to generate the comparison voltage; a bias decision control section configured to determine bias decision data for controlling a resistance value of the variable resistor section so as to bring the comparison voltage close to the original bias voltage, based on a comparison result of the comparison section; and a storage section configured to hold the bias decision data and also output the comparison voltage as a bias voltage by controlling a resistance value of the variable resistor section based on the held bias decision data, thereby generating a low-noise bias with a small area.

摘要翻译： 本发明包括：偏置起始部分，被配置为产生原始偏置电压; 比较部，被配置为比较原始偏置电压和比较电压，并输出比较结果; 电阻分压器部分，由包括具有电阻器和开关的可变电阻器部分的电阻电路组成，并被配置为产生比较电压; 偏置判定控制部，被配置为基于比较部的比较结果来确定用于控制可变电阻部的电阻值的偏置判定数据，以使比较电压接近原来的偏置电压; 以及存储部，被配置为保持偏置判定数据，并且还通过基于所保持的偏置判定数据控制可变电阻器部分的电阻值，将比较电压作为偏置电压输出，由此产生具有小面积的低噪声偏置 。

公开(公告)号：US20090051455A1

公开(公告)日：2009-02-26

申请号：US12192547

申请日：2008-08-15

申请人： Daisuke MIYASHITA

发明人： Daisuke MIYASHITA

IPC分类号： H03C3/02

CPC分类号： H03C3/40 ,  H03D3/007

摘要： A modulation/demodulation apparatus according to an embodiment of the present invention includes a sine wave generating circuit configured to output two sine waves which are orthogonal to each other and have equal amplitude, an orthogonal modulator connected to the sine wave generating circuit and configured to modulate the sine waves to generate a modulated signal, a detecting section configured to detect amplitude fluctuation in the modulated signal, a multiplying section configured to multiply the modulated signal and the amplitude fluctuation detected by the detecting section together, and an orthogonal demodulator configured to demodulate the modulated signal multiplied with the amplitude fluctuation by the multiplying section to generate a demodulated signal.

摘要翻译： 根据本发明的实施例的调制/解调装置包括：正弦波产生电路，被配置为输出彼此正交并且具有相等振幅的两个正弦波;正交调制器，连接到正弦波发生电路，并被配置为调制 所述正弦波产生调制信号，检测部，被配置为检测所述调制信号中的幅度波动;乘法部，被配置为将所述调制信号和由所述检测部检测的幅度波动相乘在一起;以及正交解调器， 调制信号与乘法部分的振幅波动相乘以产生解调信号。

公开(公告)号：US20090131099A1

公开(公告)日：2009-05-21

申请号：US12271363

申请日：2008-11-14

申请人： Daisuke MIYASHITA

发明人： Daisuke MIYASHITA

IPC分类号： H04M1/00 ,  H03F3/45

CPC分类号： H03F3/45475 ,  H03F3/45183 ,  H03F2203/45454 ,  H03F2203/45466 ,  H03F2203/45504 ,  H03F2203/45526

摘要： An amplifying device has an amplifier which amplifies an input signal supplied from an input terminal and outputs the amplified input signal, a feedback loop which has at least one of a resistive element and a capacitance connected between an output terminal of the amplifier and the input terminal, a variable current unit which adjusts a current value in accordance with a controlling signal and supplies an operating current to the amplifier, a signal analyzing unit which generates a time difference signal having a value corresponding to a slew rate of the input signal and outputs the time difference signal, and a controlling unit which generates the controlling signal in accordance with the time difference signal and outputs the controlling signal.

摘要翻译： 放大装置具有放大从输入端提供的输入信号并输出​​放大的输入信号的放大器，反馈回路具有电阻元件和连接在放大器的输出端子与输入端子之间的电容中的至少一个 ，可变电流单元，其根据控制信号调整电流值并向放大器提供工作电流;信号分析单元，其产生具有与输入信号的转换速率对应的值的时间差信号，并输出 时差信号，以及根据该时差信号生成控制信号并输出​​控制信号的控制单元。

公开(公告)号：US20070213026A1

公开(公告)日：2007-09-13

申请号：US11684128

申请日：2007-03-09

申请人： Daisuke MIYASHITA

发明人： Daisuke MIYASHITA

IPC分类号： H04B1/26

CPC分类号： H03D7/1441 ,  H03D7/1466 ,  H03D2200/0025

摘要： A semiconductor integrated circuit has a mixer circuit which includes a first MOS transistor whose source is connected to a first terminal receiving a first current signal formed by voltage-current converting a radio frequency signal, whose gate receives a first local oscillation signal via a first capacitance, and whose drain is connected to a second terminal which outputs a second current signal with the first local oscillation signal superimposed thereon, and a second MOS transistor whose source is connected to the first terminal, whose gate receives, via a second capacitance, a second local oscillation signal which is an inverted signal of the first local oscillation signal, and whose drain is connected to a third terminal which outputs a third current signal with the second local oscillation signal superimposed thereon; a third MOS transistor whose drain is connected to a first potential, and which has a conductivity type and a threshold value which are the same as those of the first MOS transistor and the second MOS transistor; a current source connected between the source of the third MOS transistor and a second potential; a voltage dividing circuit which is connected between the first potential and the second potential, and divides a voltage between the first potential and the second potential to output the divided voltage as a reference voltage; and a differential amplifier circuit whose in-phase input receives the reference voltage, whose anti-phase input receives the source potential of the third MOS transistor, and whose output is connected to the gate of the third MOS transistor, wherein the output voltage of the differential amplifier circuit is applied to the gate of the first MOS transistor via a first resistor, and to the gate of the second MOS transistor via a second resistor, and wherein DC voltages of the drain and the source of the first and second MOS transistors are controlled to be equal to the reference voltage.