公开(公告)号：US06580126B1

公开(公告)日：2003-06-17

申请号：US09709582

申请日：2000-11-13

申请人： Masahiko Suzumura ,  Hitomichi Takano ,  Yuji Suzuki ,  Takashi Kishida ,  Yoshiki Hayasaki ,  Yoshifumi Shirai ,  Takeshi Yoshida ,  Yasunori Miyamoto

发明人： Masahiko Suzumura ,  Hitomichi Takano ,  Yuji Suzuki ,  Takashi Kishida ,  Yoshiki Hayasaki ,  Yoshifumi Shirai ,  Takeshi Yoshida ,  Yasunori Miyamoto

IPC分类号： H01L2976

CPC分类号： H01L29/7824 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L27/088 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0696 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48237 ,  H01L2224/48257 ,  H01L2224/49 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/12036 ,  H01L2924/12041 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/00 ,  H01L2224/45099

摘要： A solid state relay composed of a series connected pair of LDMOSFETs has a minimized output capacitance. Each LDMOSFET is configured to have a silicon layer of a first conductive type, a drain region of the first conductive type diffused in the top surface of the silicon layer, a well region of a second conductive type diffused in the silicon layer in a laterally spaced relation from the drain region, and a source region of the first conductive type diffused within the well region to define a channel extending between the source region and a confronting edge of the well region along the top surface of the silicon layer. Each LDMOSFET is of an SOI (Silicon-On-Insulator) structure composed of a silicon substrate placed on a supporting plate, a buried oxide layer on the silicon substrate, and the silicon layer on the buried oxide layer. The well region is diffused over the full depth of the silicon layer to have its bottom in contact with the buried oxide layer, so that the well region forms with the silicon layer a P-N interface only at a small area adjacent the channel. Because of this reduced P-N interface and also because of the buried oxide layer exhibiting a much lower inductive capacitance than the silicon layer, it is possible to greatly reduce a drain-source capacitance for minimizing the output capacitance of the relay in the non-conductive condition.

公开(公告)号：US5780900A

公开(公告)日：1998-07-14

申请号：US733164

申请日：1996-10-17

申请人： Yuji Suzuki ,  Hitomichi Takano ,  Masahiko Suzumura ,  Yoshiki Hayasaki ,  Takashi Kishida ,  Yoshifumi Shirai

发明人： Yuji Suzuki ,  Hitomichi Takano ,  Masahiko Suzumura ,  Yoshiki Hayasaki ,  Takashi Kishida ,  Yoshifumi Shirai

IPC分类号： H01L29/06 ,  H01L29/08 ,  H01L29/78 ,  H01L29/786 ,  H01L29/10

CPC分类号： H01L29/7824 ,  H01L29/0873 ,  H01L29/78624 ,  H01L29/0657 ,  H01L29/0878 ,  H01L29/402

摘要： A thin film transistor of SOI (Silicon-On-Insulator) type includes a buried oxide layer formed on a semiconductor substrate, a silicon layer of a first conductive type formed on the buried oxide layer, and an upper oxide layer formed on the silicon layer. The silicon layer has a body region of a second conductive type, source region of the first conductive type, drain region of the first conductive type, and a drift region of the first conductive type. The silicon layer is formed with a first portion of a thickness T1 in which the doping region is formed, and a second portion of a thickness T2 in which the body region is formed to reach the buried oxide layer. When the thicknesses T1 and T2 are determined so as to satisfy the relationships: 0.4 .mu.m

摘要翻译： SOI（绝缘体上硅）型薄膜晶体管包括在半导体衬底上形成的掩埋氧化物层，形成在掩埋氧化物层上的第一导电类型的硅层和形成在硅层上的上部氧化物层 。 硅层具有第二导电类型的主体区域，第一导电类型的源极区域，第一导电类型的漏极区域和第一导电类型的漂移区域。 硅层形成有其中形成有掺杂区域的厚度T1的第一部分和形成有体区以到达掩埋氧化物层的厚度T2的第二部分。 当厚度T1和T2被确定为满足以下关系：0.4μm

公开(公告)号：US06448620B2

公开(公告)日：2002-09-10

申请号：US09741812

申请日：2000-12-22

申请人： Yoshiki Hayasaki ,  Hitomichi Takano ,  Masahiko Suzumura ,  Yuji Suzuki ,  Yoshifumi Shirai ,  Takashi Kishida ,  Takeshi Yoshida ,  Takaaki Yoshihara

发明人： Yoshiki Hayasaki ,  Hitomichi Takano ,  Masahiko Suzumura ,  Yuji Suzuki ,  Yoshifumi Shirai ,  Takashi Kishida ,  Takeshi Yoshida ,  Takaaki Yoshihara

IPC分类号： H01L2701

CPC分类号： H01L29/7824 ,  H01L29/0878 ,  H01L29/66681 ,  H01L29/78624

摘要： To provide a semiconductor device having a large allowable current, a demanded withstand voltage, and small output capacitance and resistance, the semiconductor device comprises a semiconductor layer formed on a semiconductor substrate, and the semiconductor layer includes a first conductivity type-drain region, a second conductivity type-well region apart from the drain region, a first conductivity type-source region in the well region apart from one end of the well region on the side of the drain region, a first conductivity type-drift region formed between one end of the well region and the drain region and in contact with the well region and the drain region, respectively, and a gate electrode formed spaced a gate oxide layer and on the well region located between the drift region and the source region; and the impurity concentration of the drift region decreases in the lateral direction and also in the vertical direction, respectively, as the distance from the drain region increases.

摘要翻译： 为了提供具有大容许电流，所要求的耐受电压和小的输出电容和电阻的半导体器件，半导体器件包括形成在半导体衬底上的半导体层，并且半导体层包括第一导电类型 - 漏极区域， 与漏极区分离的第二导电类型 - 阱区，在与漏极区一侧的阱区的一端分开的阱区中的第一导电型 - 源极区，形成在漏极区的一端 和与阱区和漏极区分别接触的阱区和形成在栅极氧化物层之间以及位于漂移区和源极区之间的阱区上的栅极; 随着距离漏极区域的距离增加，漂移区域的杂质浓度分别在横向和垂直方向上减小。

公开(公告)号：US06373101B1

公开(公告)日：2002-04-16

申请号：US09709528

申请日：2000-11-13

申请人： Masahiko Suzumura ,  Hitomichi Takano ,  Yuji Suzuki ,  Takashi Kishida ,  Yoshiki Hayasaki ,  Yoshifumi Shirai ,  Takeshi Yoshida ,  Yasunori Miyamoto

发明人： Masahiko Suzumura ,  Hitomichi Takano ,  Yuji Suzuki ,  Takashi Kishida ,  Yoshiki Hayasaki ,  Yoshifumi Shirai ,  Takeshi Yoshida ,  Yasunori Miyamoto

IPC分类号： H01L2976

CPC分类号： H01L29/7824 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L27/088 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0696 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48237 ,  H01L2224/48257 ,  H01L2224/49 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/12036 ,  H01L2924/12041 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/00 ,  H01L2224/45099

摘要： A solid state relay composed of a series connected pair of LDMOSFETs has a minimized output capacitance. Each LDMOSFET is configured to have a silicon layer of a first conductive type, a drain region of the first conductive type diffused in the top surface of the silicon layer, a well region of a second conductive type diffused in the silicon layer in a laterally spaced relation from the drain region, and a source region of the first conductive type diffused within the well region to define a channel extending between the source region and a confronting edge of the well region along the top surface of the silicon layer. Each LDMOSFET is of an SOI (Silicon-On-Insulator) structure composed of a silicon substrate placed on a supporting plate, a buried oxide layer on the silicon substrate, and the silicon layer on the buried oxide layer. The well region is diffused over the full depth of the silicon layer to have its bottom in contact with the buried oxide layer, so that the well region forms with the silicon layer a P-N interface only at a small area adjacent the channel. Because of this reduced P-N interface and also because of the buried oxide layer exhibiting a much lower inductive capacitance than the silicon layer, it is possible to greatly reduce a drain-source capacitance for minimizing the output capacitance of the relay in the non-conductive condition.

摘要翻译： 由串联连接的LDMOSFET组成的固态继电器具有最小的输出电容。 每个LDMOSFET被配置为具有第一导电类型的硅层，第一导电类型的漏极区域扩散在硅层的顶表面中，第二导电类型的阱区域在硅层中以横向间隔开地扩散 与漏区域的关系以及在阱区域内扩散的第一导电类型的源极区域，以限定沿着硅层的顶表面在源极区域和阱区域的相对边缘之间延伸的沟道。 每个LDMOSFET是由放置在支撑板上的硅衬底，硅衬底上的掩埋氧化物层和掩埋氧化物层上的硅层组成的SOI（绝缘体上硅）结构。 阱区域在硅层的整个深度上扩散以使其底部与掩埋氧化物层接触，使得阱区域仅在邻近通道的小区域处与硅层形成P-N界面。 由于这种减小的PN接口，并且由于掩埋氧化物层具有比硅层更低的电感性电容，因此可以大大减小漏 - 源电容，以使在非导电条件下继电器的输出电容最小化 。

公开(公告)号：US06211551B1

公开(公告)日：2001-04-03

申请号：US09105464

申请日：1998-06-26

申请人： Masahiko Suzumura ,  Hitomichi Takano ,  Yuji Suzuki ,  Takashi Kishida ,  Yoshiki Hayasaki ,  Yoshifumi Shirai ,  Takeshi Yoshida ,  Yasunori Miyamoto

发明人： Masahiko Suzumura ,  Hitomichi Takano ,  Yuji Suzuki ,  Takashi Kishida ,  Yoshiki Hayasaki ,  Yoshifumi Shirai ,  Takeshi Yoshida ,  Yasunori Miyamoto

IPC分类号： H01L2976

CPC分类号： H01L29/7824 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L27/088 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0696 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48237 ,  H01L2224/48257 ,  H01L2224/49 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/12036 ,  H01L2924/12041 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/00 ,  H01L2224/45099

摘要： A solid state relay composed of a series connected pair of LDMOSFETs has a minimized output capacitance. Each LDMOSFET is configured to have a silicon layer of a first conductive type, a drain region of the first conductive type diffused in the top surface of the silicon layer, a well region of a second conductive type diffused in the silicon layer in a laterally spaced relation from the drain region, and a source region of the first conductive type diffused within the well region to define a channel extending between the source region and a confronting edge of the well region along the top surface of the silicon layer. Each LDMOSFET is of an SOI (Silicon-On-Insulator) structure composed of a silicon substrate placed on a supporting plate, a buried oxide layer on the silicon substrate, and the silicon layer on the buried oxide layer. The well region is diffused over the full depth of the silicon layer to have its bottom in contact with the buried oxide layer, so that the well region forms with the silicon layer a P-N interface only at a small area adjacent the channel. Because of this reduced P-N interface and also because of the buried oxide layer exhibiting a much lower inductive capacitance than the silicon layer, it is possible to greatly reduce a drain-source capacitance for minimizing the output capacitance of the relay in the non-conductive condition.

摘要翻译： 由串联连接的LDMOSFET组成的固态继电器具有最小的输出电容。 每个LDMOSFET被配置为具有第一导电类型的硅层，第一导电类型的漏极区域扩散在硅层的顶表面中，第二导电类型的阱区域在硅层中以横向间隔开地扩散 与漏区域的关系以及在阱区域内扩散的第一导电类型的源极区域，以限定沿着硅层的顶表面在源极区域和阱区域的相对边缘之间延伸的沟道。 每个LDMOSFET是由放置在支撑板上的硅衬底，硅衬底上的掩埋氧化物层和掩埋氧化物层上的硅层组成的SOI（绝缘体上硅）结构。 阱区域在硅层的整个深度上扩散以使其底部与掩埋氧化物层接触，使得阱区域仅在邻近通道的小区域处与硅层形成P-N界面。 由于这种减小的PN接口，并且由于掩埋氧化物层具有比硅层更低的电感性电容，因此可以大大减小漏 - 源电容，以使在非导电条件下继电器的输出电容最小化 。

公开(公告)号：US20070128831A1

公开(公告)日：2007-06-07

申请号：US10572554

申请日：2004-09-12

申请人： Naomasa Oka ,  Hiroshi Harada ,  Jun Ogihara ,  Hiroshi Fukshima ,  Hiroshi Noge ,  Yuji Suzuki ,  Kiyohiko Kawano ,  Takaaki Yoshihara ,  Masahiko Suzumura

发明人： Naomasa Oka ,  Hiroshi Harada ,  Jun Ogihara ,  Hiroshi Fukshima ,  Hiroshi Noge ,  Yuji Suzuki ,  Kiyohiko Kawano ,  Takaaki Yoshihara ,  Masahiko Suzumura

IPC分类号： H01L21/30

CPC分类号： G02B26/0816 ,  B81B3/0086 ,  B81B2201/033 ,  B81B2201/045 ,  B81C1/00484 ,  B81C2201/0109 ,  B81C2201/019 ,  G02B6/3516 ,  G02B6/3518 ,  G02B6/3546 ,  G02B6/355 ,  G02B6/357 ,  G02B6/3584 ,  H02N1/008

摘要： A process for fabricating a micro-electro-mechanical system (MEMS) composed of fixed components fixedly supported on a lower substrate and movable components movably supported on the lower substrate. The process utilizes an upper substrate separate from the lower substrate. The upper substrate is selectively etched in its top layer to form therein a plurality of posts which project commonly from a bottom layer of the upper substrate. The posts include the fixed components to be fixed to the lower substrate and the movable components which are resiliently supported only to one or more of the fixed components to be movable relative to the fixed components. The lower substrate is formed in its top surface with at least one recess. The upper substrate is then bonded to the top of the lower substrate upside down in such a manner as to place the fixed components directly on the lower substrate and to place the movable components upwardly of the recess. Finally, the bottom layer of the upper substrate is removed to release the movable components from the bottom layer for floating the movable components above the recess and allowing them to move relative to the lower substrate, while keeping the fixed components fixed to the top of the lower substrate.

摘要翻译： 一种用于制造由固定地支撑在下基板上的固定部件和可移动地支撑在下基板上的可移动部件的微机电系统（MEMS）的制造方法。 该方法利用与下基板分开的上基板。 在其顶层中选择性地蚀刻上基板，以在其中形成多个从上基板的底层共同突出的柱。 支柱包括要固定到下基板的固定部件和仅弹性地支撑到一个或多个固定部件以相对于固定部件可移动的可动部件。 下基板在其顶表面上形成有至少一个凹部。 然后将上基板以这样的方式上下连接到下基板的顶部，以将固定部件直接放置在下基板上并将可移动部件放置在凹部的上方。 最后，去除上基板的底层以从底层释放可移动部件，用于使可移动部件浮动在凹部上方并允许​​它们相对于下基板移动，同时保持固定部件固定在 下基板。

公开(公告)号：US07422928B2

公开(公告)日：2008-09-09

申请号：US10572554

申请日：2004-09-12

申请人： Naomasa Oka ,  Hiroshi Harada ,  Jun Ogihara ,  Hiroshi Fukshima ,  Hiroshi Noge ,  Yuji Suzuki ,  Kiyohiko Kawano ,  Takaaki Yoshihara ,  Masahiko Suzumura

发明人： Naomasa Oka ,  Hiroshi Harada ,  Jun Ogihara ,  Hiroshi Fukshima ,  Hiroshi Noge ,  Yuji Suzuki ,  Kiyohiko Kawano ,  Takaaki Yoshihara ,  Masahiko Suzumura

IPC分类号： H01L21/00 ,  H02N1/00

CPC分类号： G02B26/0816 ,  B81B3/0086 ,  B81B2201/033 ,  B81B2201/045 ,  B81C1/00484 ,  B81C2201/0109 ,  B81C2201/019 ,  G02B6/3516 ,  G02B6/3518 ,  G02B6/3546 ,  G02B6/355 ,  G02B6/357 ,  G02B6/3584 ,  H02N1/008

摘要： A process for fabricating a micro-electro-mechanical system (MEMS) composed of fixed components fixedly supported on a lower substrate and movable components movably supported on the lower substrate. The process utilizes an upper substrate separate from the lower substrate. The upper substrate is selectively etched in its top layer to form therein a plurality of posts which project commonly from a bottom layer of the upper substrate. The posts include the fixed components to be fixed to the lower substrate and the movable components which are resiliently supported only to one or more of the fixed components to be movable relative to the fixed components. The lower substrate is formed in its top surface with at least one recess. The upper substrate is then bonded to the top of the lower substrate upside down in such a manner as to place the fixed components directly on the lower substrate and to place the movable components upwardly of the recess. Finally, the bottom layer of the upper substrate is removed to release the movable components from the bottom layer for floating the movable components above the recess and allowing them to move relative to the lower substrate, while keeping the fixed components fixed to the top of the lower substrate.

摘要翻译： 一种用于制造由固定地支撑在下基板上的固定部件和可移动地支撑在下基板上的可移动部件的微机电系统（MEMS）的制造方法。 该方法利用与下基板分开的上基板。 在其顶层中选择性地蚀刻上基板，以在其中形成多个从上基板的底层共同突出的柱。 支柱包括要固定到下基板的固定部件和仅弹性地支撑到一个或多个固定部件以相对于固定部件可移动的可动部件。 下基板在其顶表面上形成有至少一个凹部。 然后将上基板以这样的方式上下连接到下基板的顶部，以将固定部件直接放置在下基板上并将可移动部件放置在凹部的上方。 最后，去除上基板的底层以从底层释放可移动部件，用于使可移动部件浮动在凹部上方并允许​​它们相对于下基板移动，同时保持固定部件固定在 下基板。

公开(公告)号：US11084682B2

公开(公告)日：2021-08-10

申请号：US16127554

申请日：2018-09-11

申请人： Takahiro Watanabe ,  Tomohiro Furuhashi ,  Michitaka Suzuki ,  Tomomichi Hoshino ,  Yuji Suzuki ,  Satoshi Saito ,  Takao Watanabe

发明人： Takahiro Watanabe ,  Tomohiro Furuhashi ,  Michitaka Suzuki ,  Tomomichi Hoshino ,  Yuji Suzuki ,  Satoshi Saito ,  Takao Watanabe

IPC分类号： B65H45/20 ,  B65H45/101 ,  B65H45/14 ,  G03G15/00 ,  G03G21/16

摘要： A sheet processing apparatus includes: a second conveying roller pair that receives and conveys a sheet conveyed by a first conveying roller pair; a first folding roller pair that forms a first fold on the sheet; and a first rotation unit capable of rotating the second conveying roller pair and the first folding roller pair. One roller of the second conveying roller pair and one roller of the first folding roller pair are a common roller shared therebetween. The second conveying roller pair causes the sheet to be deflected and guided to the first folding roller pair, and the first folding roller pair forms the first fold on the deflected sheet by rotating the first rotation unit in a certain direction in a state in which the sheet is held by the first conveying roller pair and the second conveying roller pair.

公开(公告)号：US20180024466A1

公开(公告)日：2018-01-25

申请号：US15709145

申请日：2017-09-19

申请人： NOBUO TAKAMI ,  Noriyuki Kimura ,  Eisuke Hori ,  Hideki Kimura ,  Kenji Kikuchi ,  Yuji Suzuki

发明人： NOBUO TAKAMI ,  Noriyuki Kimura ,  Eisuke Hori ,  Hideki Kimura ,  Kenji Kikuchi ,  Yuji Suzuki

IPC分类号： G03G15/08 ,  G03G21/16

CPC分类号： G03G15/0879 ,  G03G15/0863 ,  G03G15/0872 ,  G03G15/0886 ,  G03G21/1647 ,  G03G2215/0665 ,  G03G2215/0668 ,  G03G2215/0692 ,  G03G2215/0695 ,  G03G2215/0697

摘要： A system with a container including a protrusion, and a receiver to receive the container. The receiver includes a slide block that is movable relative to a body of the receiver, the slide block including two surfaces, a first surface, initially contacted by the protrusion of the container during insertion of the container into the receiver, having a first slope to resist movement of the container towards the receiver, and a second surface, subsequently contacted by the protrusion of the container during the insertion of the container into the receiver, having a second slope to interact with the protrusion of the container to assist movement of the container towards the receiver. This construction provides the user with a changing insertion force to indicate proper mounting of the container.

公开(公告)号：US09778596B2

公开(公告)日：2017-10-03

申请号：US15379985

申请日：2016-12-15

申请人： Nobuo Takami ,  Noriyuki Kimura ,  Eisuke Hori ,  Hideki Kimura ,  Kenji Kikuchi ,  Yuji Suzuki

发明人： Nobuo Takami ,  Noriyuki Kimura ,  Eisuke Hori ,  Hideki Kimura ,  Kenji Kikuchi ,  Yuji Suzuki

IPC分类号： G03G15/08

CPC分类号： G03G15/0879 ,  G03G15/0863 ,  G03G15/0872 ,  G03G15/0886 ,  G03G21/1647 ,  G03G2215/0665 ,  G03G2215/0668 ,  G03G2215/0692 ,  G03G2215/0695 ,  G03G2215/0697

摘要： A system with a container including a protrusion, and a receiver to receive the container. The receiver includes a slide block that is movable relative to a body of the receiver, the slide block including two surfaces, a first surface, initially contacted by the protrusion of the container during insertion of the container into the receiver, having a first slope to resist movement of the container towards the receiver, and a second surface, subsequently contacted by the protrusion of the container during the insertion of the container into the receiver, having a second slope to interact with the protrusion of the container to assist movement of the container towards the receiver. This construction provides the user with a changing insertion force to indicate proper mounting of the container.