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49 条记录 (耗时 0.022 秒)

    Serial data transfer circuit for a semiconductor memory device
    1.
    发明授权
    Serial data transfer circuit for a semiconductor memory device 失效
    用于半导体存储器件的串行数据传输电路

    公开(公告)号：US4995003A

    公开(公告)日：1991-02-19

    申请号：US289115

    申请日：1988-12-23

    申请人： Yuji Watanabe ,  Haruki Toda ,  Hiroshi Sahara ,  Shigeo Ohshima

    发明人： Yuji Watanabe ,  Haruki Toda ,  Hiroshi Sahara ,  Shigeo Ohshima

    IPC分类号： G11C11/417 ,  G06F5/08 ,  G11C7/10 ,  G11C11/401 ,  G11C11/409 ,  G11C11/41

    CPC分类号： G06F5/08 ,  G11C7/1006

    摘要： A data transfer circuit is connected between first and second circuits so as to control data transfers therebetween. The data transfer circuit comprises first and second latch circuits for latching data in response to first and second latch control signals, respectively, a first data transfer gate connected between the first circuit and the first latch circuit and responsive to a first gate control signal to make electrical connection or disconnection therebetween, a second transfer gate connected between the first and second data latch circuits and responsive to a second gate control signal to make electrical connection or disconnection therebetween, and a third data transfer gate connected between the second data latch circuit and the second circuit and responsive to a third gate control signal to make electrical connection or disconnection therebetween. After data is transferred from the first circuit to the first data latch circuit, the data can be transferred from the data latch circuit to the second data latch circuit even if the data in the data first circuit disappears. The third data transfer gate can be opened to transfer data from the second data latch circuit to the second circuit.

    Semiconductor memory having a barrier transistor between a bit line and a sensing amplifier
    2.
    发明授权
    Semiconductor memory having a barrier transistor between a bit line and a sensing amplifier 失效
    具有在位线和感测放大器之间的势垒晶体管的半导体存储器

    公开(公告)号：US4794569A

    公开(公告)日：1988-12-27

    申请号：US863190

    申请日：1986-05-14

    申请人： Hiroshi Sahara ,  Haruki Toda ,  Shigeo Ohshima

    发明人： Hiroshi Sahara ,  Haruki Toda ,  Shigeo Ohshima

    IPC分类号： G11C11/409 ,  G11C11/4094 ,  G11C11/4096 ,  G11C7/00

    CPC分类号： G11C11/4096 ,  G11C11/4094

    摘要： In this invention, in a sensing circuit of a dynamic memory, barrier transistors are provided between the bit lines and the sensing amplifier. A circuit is provided that, on sensing and on data transfer, changes the gate potential of the barrier transistors so that during the sensing operation the barrier transistors are temporarily turned OFF, so that sensing can be carried out with high sensitivity, as the sensing system is not affected by the parasitic capacitance of the bit lines, while, on data transfer to the input/output lines, the gate potential of the barrier transistors is raised to a level greater than a value reached by adding the threshold value of the MOS transistors to the power source voltage, so that the conductance of the barrier transistors is increased, thereby speeding up the presensing of the input/output lines in the sensing circuit.

    摘要翻译： 在本发明中，在动态存储器的感测电路中，在位线和感测放大器之间设置有阻挡晶体管。 提供了一种电路，其在感测和数据传输时改变势垒晶体管的栅极电位，使得在感测操作期间，阻挡晶体管暂时断开，使得可以以高灵敏度进行感测，作为感测系统 不受位线的寄生电容的影响，而在向输入/输出线路传输数据时，势垒晶体管的栅极电位升高到大于通过将MOS晶体管的阈值相加而达到的值 以使得阻挡晶体管的电导增加，从而加速感测电路中的输入/输出线的预置。

    Serially-accessed type memory device for providing an interleaved data read operation
    3.
    发明授权
    Serially-accessed type memory device for providing an interleaved data read operation 失效
    用于提供交错数据读取操作的串行访问型存储器件

    公开(公告)号：US5237532A

    公开(公告)日：1993-08-17

    申请号：US794668

    申请日：1991-11-18

    申请人： Hiroshi Sahara ,  Haruki Toda ,  Shigeo Ohshima

    发明人： Hiroshi Sahara ,  Haruki Toda ,  Shigeo Ohshima

    IPC分类号： G11C7/10

    CPC分类号： G11C7/103

    摘要： In a semiconductor memory having a column-direction serial access function, two systems of circuits for selecting and fetching data are provided. A circuit operation is alternately performed such that one system is set up while the other system is accessed, thereby reducing a cycle time for a data selecting/fetching operation.

    摘要翻译： 在具有列方向串行访问功能的半导体存储器中，提供用于选择和取出数据的两个电路系统。 交替执行电路操作，使得在另一个系统被访问时建立一个系统，从而减少数据选择/取出操作的周期时间。

    Semiconductor memory system
    5.
    发明授权
    Semiconductor memory system 失效
    半导体存储系统

    公开(公告)号：US5107464A

    公开(公告)日：1992-04-21

    申请号：US480902

    申请日：1990-02-16

    申请人： Hiroshi Sahara ,  Haruki Toda ,  Shigeo Ohshima

    发明人： Hiroshi Sahara ,  Haruki Toda ,  Shigeo Ohshima

    IPC分类号： G11C11/401 ,  G11C29/00 ,  G11C29/04

    CPC分类号： G11C29/846

    摘要： In a semiconductor memory system of the serial column access type, a redundant column is used for replacing a defective column. Redundant data lines are connected to the redundant column through a redundant column selection gate. A defective address detection circuit detects the address of a defective column to enable the redundant column selection gate. An address counter is provided for a defective address detection circuit. A redundant column selection circuit selects the redundant column in response to a detection signal from the defective address detection circuit. A data line switching circuit switches, in redundant column select mode, the data lines connecting to a data input/output drive circuit from said regular data lines to the redundant data lines. With this circuit arrangement, in a redundant column select mode, the regular data lines are separated from the data input/output drive circuit. Therefore, even if a shift register constituting a regular column selection circuit operates and the defective column selection gate is enabled to set up a connection of the defective column to the regular data lines, the error data from the defective column is never output. Further, the shift register is operable irrespective of the defective column detection.

    Flip-flop circuit
    7.
    发明授权
    Flip-flop circuit 失效
    触发电路

    公开(公告)号：US4678934A

    公开(公告)日：1987-07-07

    申请号：US884629

    申请日：1986-07-11

    申请人： Koichi Magome ,  Haruki Toda ,  Hiroyuki Koinuma ,  Hiroshi Sahara ,  Kiminobu Suzuki ,  Shigeo Ohshima ,  Kenji Komatsu

    发明人： Koichi Magome ,  Haruki Toda ,  Hiroyuki Koinuma ,  Hiroshi Sahara ,  Kiminobu Suzuki ,  Shigeo Ohshima ,  Kenji Komatsu

    IPC分类号： G11C11/40 ,  G11C8/06 ,  H03K3/356 ,  H03K3/26 ,  G11C7/00 ,  H03K17/687 ,  H03K19/094

    CPC分类号： H03K3/356026 ,  G11C8/06

    摘要： A flip-flop circuit has a power terminal set at 5 V, first and second output terminals, a latch section for charging one of the first and second terminals to 5 V and discharging the other one of the first and second terminals to 0 V in accordance with an input signal, a first MOS transistor having a current path connected between the power and first output terminals, a second MOS transistor for charging the gate of the first MOS transistor while the potential of the second output terminal is changed from 5 V to 0 V, and a capacitor for bootstrapping the gate potential of the first MOS transistor to turn on the first MOS transistor. The flip-flop circuit further includes a third MOS transistor, having a current path connected between the gate of the first MOS transistor and the first output terminal and a gate connected to the first output terminal, for charging the gate of the first MOS transistor when the gate potential of the first MOS transistor is dropped a predetermined level in comparison with that of the first output terminal.

    摘要翻译： 触发器电路具有设置在5V的电源端子，第一和第二输出端子，用于将第一和第二端子中的一个充电至5V并将第一和第二端子中的另一个放电至0V的锁存部分 根据输入信号，具有连接在电源和第一输出端子之间的电流路径的第一MOS晶体管，第二MOS晶体管，用于对第一MOS晶体管的栅极充电，同时第二输出端子的电位从5V变为 0V，以及用于自举第一MOS晶体管的栅极电位以使第一MOS晶体管导通的电容器。 触发器电路还包括第三MOS晶体管，其具有连接在第一MOS晶体管的栅极和第一输出端子之间的电流路径和连接到第一输出端子的栅极，用于对第一MOS晶体管的栅极充电， 与第一输出端子相比，第一MOS晶体管的栅极电位下降到预定水平。

    Semiconductor memory system
    8.
    发明授权
    Semiconductor memory system 失效
    半导体存储系统

    公开(公告)号：US4951253A

    公开(公告)日：1990-08-21

    申请号：US264741

    申请日：1988-10-31

    申请人： Hiroshi Sahara ,  Haruki Toda ,  Shigeo Oshima

    发明人： Hiroshi Sahara ,  Haruki Toda ,  Shigeo Oshima

    IPC分类号： G11C11/401 ,  G11C29/00 ,  G11C29/04

    CPC分类号： G11C29/846

    摘要： In a semiconductor memory system of the serial column access type, a redundant column is used for replacing a defective column. Redundant data lines are connected to the redundant column through a redundant column selection gate. A defective address detection circuit detects the address of a defective column to enable the redundant column selection gate. An address counter is provided for a defective address detection circuit. A redundant column selection circuit selects the redundant column in response to a detection signal from the defective address detection circuit. A data line switching circuit switches, in redundant column select mode, the data lines connecting to a data input/output drive circuit from said regular data lines to the redundant data lines. With this circuit arrangement, in a redundant column select mode, the regular data lines are separated from the data input/output drive circuit. Therefore, even if a shift register constituting a regular column selection circuit operates and the defective column selection gate is enabled to set up a connection of the defective column to the regular data lines, the error data from the defective column is never output. Further, the shift register is operable irrespective of the defecting column detection.

    Semiconductor memory device with column redundancy
    9.
    发明授权
    Semiconductor memory device with column redundancy 失效
    具有列冗余的半导体存储器件

    公开(公告)号：US5168468A

    公开(公告)日：1992-12-01

    申请号：US789036

    申请日：1991-11-07

    申请人： Koichi Magome ,  Hiroshi Sahara ,  Haruki Toda

    发明人： Koichi Magome ,  Hiroshi Sahara ,  Haruki Toda

    IPC分类号： G11C11/401 ,  G11C11/407 ,  G11C11/418 ,  G11C29/00 ,  G11C29/04

    CPC分类号： G11C29/818

    摘要： A semiconductor memory device comprises a memory cell array, a redundant memory cell array, bit line pairs, spare bit line pairs, a column address information storage circuit having stored therein information of a column address of a faulty cell and a column address of a spare cell, column decoders, a first column selecting gate for connecting one of the bit line pairs and first data output line pairs, a second column selecting gate for connecting one of the bit line pairs and a second data output line pair, a spare column decoder for selecting a third or a fourth column selecting line, a third column selecting gate for connecting the spare bit line pairs and the first data output line pairs, a fourth column selecting gate for connecting the spare bit line pairs and the second data output line pair, a first buffer for selecting two data and amplifying and outputting, a second buffer for amplifying and outputting data from the second data output line pair, and a register for storing therein data from the first and/or second buffers.

    摘要翻译： 半导体存储器件包括存储单元阵列，冗余存储单元阵列，位线对，备用位线对，列存储有故障单元的列地址的信息和备用列列地址的列地址信息存储电路 单元，列解码器，用于连接位线对和第一数据输出线对中的一个的第一列选择栅极，用于连接位线对之一和第二数据输出线对的第二列选择栅极，备用列解码器 用于选择第三或第四列选择线，用于连接备用位线对和第一数据输出线对的第三列选择栅极，用于连接备用位线对和第二数据输出线对的第四列选择栅极 用于选择两个数据并放大和输出的第一缓冲器，用于放大和输出来自第二数据输出线对的数据的第二缓冲器，以及用于存储 控制来自第一和/或第二缓冲器的数据。