公开(公告)号：US20050091458A1

公开(公告)日：2005-04-28

申请号：US10800349

申请日：2004-03-12

申请人： Yumi Sato ,  Fumio Sudo ,  Yasumasa Nakada

发明人： Yumi Sato ,  Fumio Sudo ,  Yasumasa Nakada

IPC分类号： G06F12/08 ,  G06F12/10 ,  G06F13/28

CPC分类号： G06F12/0831 ,  G06F12/0888

摘要： The present invention of a storage control apparatus which is connected to a host bus connected to a CPU (Central Processing Unit), a peripheral bus connected to at least one IP (Intellectual Property), and a system memory and controls DMA (Direct Memory Access) transfer from the IP to the system memory, having: an address map judgment section which judges whether an address given from one of the peripheral bus and the host bus indicates a memory area managed by the storage control apparatus in the system memory; a memory control section which controls data transfer to/from the system memory; a TLB (Translation Look-aside Buffer) information holding section which holds address information that indicates an area cacheable by the CPU; an address judgment section which judges on the basis of the address information held by the TLB information holding section whether the address given from one of the peripheral bus and the host bus indicates the area cacheable by the CPU; and a snoop address control section which, when it is judged on the basis of a judgment result from the address judgment section that the CPU needs to be notified of the address, executes notification through the host bus.

摘要翻译： 连接到连接到CPU（中央处理单元）的主机总线，连接到至少一个IP（知识产权）的外围总线以及系统存储器并且控制DMA（直接存储器访问）的存储控制装置的本发明 ）从IP传送到系统存储器，具有：地址映射判断部，判断从外围总线和主机总线中的一个给出的地址是否表示由系统存储器中的存储控制装置管理的存储区域; 存储器控制部分，其控制到/从系统存储器传送的数据; 信息保持部分，其保存指示可由CPU缓存的区域的地址信息; 地址判定部，其根据由TLB信息保持部所保持的地址信息判断从外围总线和主机总线之一给出的地址是否表示CPU可高速缓存的区域; 以及侦听地址控制部，其基于来自所述地址判断部的判定结果判断为需要通知所述CPU的地址，通过所述主机总线执行通知。

公开(公告)号：US06931495B2

公开(公告)日：2005-08-16

申请号：US10256079

申请日：2002-09-27

申请人： Yasumasa Nakada

发明人： Yasumasa Nakada

IPC分类号： G06F12/08 ,  G06F13/28 ,  G06F12/00

CPC分类号： G06F12/0835 ,  G06F12/0804

摘要： A processor system, comprising: a processor having a function to write back data stored in a cache memory to an external memory in units of a cache line formed of a plurality of words; a small unit dirty information storing part which stores non-write-back information in units of address range smaller than that of the cache line, the information indicating that the write-back to the external memory is not yet performed; a mode information storing part which stores specific mode flag information which is set or reset by software in order to determine whether or not to be in a mode for not performing unnecessary write-back operation; and; and a write-back determining part which decides whether or not to write back a certain cache line before performing the DMA transfer based on the non-write-back information, when the specific mode flag is set and the write-back of the cache line is instructed.

摘要翻译： 一种处理器系统，包括：处理器，具有将以多个单词形成的高速缓存行为单位将存储在高速缓冲存储器中的数据写回到外部存储器的功能; 小地址范围小于高速缓存行的地址范围的非回写信息的小单位脏信息存储部，表示还没有对外部存储器进行写回的信息; 模式信息存储部分，其存储通过软件设置或重置的特定模式标志信息，以便确定是否处于不执行不必要的回写操作的模式; 和; 以及回写确定部件，当所述特定模式标志被设置并且所述高速缓存行的写回时，基于所述非回写信息来决定是否在执行所述DMA传送之前写回所述高速缓存行 被指示