公开(公告)号：US20090278170A1

公开(公告)日：2009-11-12

申请号：US12116231

申请日：2008-05-07

申请人： Yun-Chi Yang ,  Jih-Shun Chiang ,  Cheng-Li Lin ,  Ju-Ping Chen ,  Kuan-Cheng Su

发明人： Yun-Chi Yang ,  Jih-Shun Chiang ,  Cheng-Li Lin ,  Ju-Ping Chen ,  Kuan-Cheng Su

IPC分类号： H01L29/778 ,  H01L21/336

CPC分类号： H01L29/66636 ,  H01L21/28518 ,  H01L21/3148 ,  H01L29/456 ,  H01L29/665

摘要： A method for manufacturing a semiconductor device includes providing a substrate having at least a gate structure formed thereon, forming LDDs in the substrate respectively at two side of the gate structure and a spacer at sidewalls of the gate structure, forming a source/drain in the substrate at two side of the gate structure, performing ant etching process to form recesses respectively in the source/drain, forming a barrier layer in the recesses; and performing a salicide process.

摘要翻译： 一种制造半导体器件的方法包括提供至少形成有栅极结构的衬底，分别在栅极结构的两侧在衬底中形成LDD，在栅极结构的侧壁形成间隔物，在栅极结构的侧壁形成源极/漏极 基板在栅极结构的两侧，进行蚂蚁蚀刻处理以分别在源极/漏极中形成凹槽，在凹部中形成阻挡层; 并执行自杀过程。

公开(公告)号：US20080194070A1

公开(公告)日：2008-08-14

申请号：US12108519

申请日：2008-04-24

申请人： Hung-Lin Shih ,  Jih-Shun Chiang ,  Hsien-Liang Meng

发明人： Hung-Lin Shih ,  Jih-Shun Chiang ,  Hsien-Liang Meng

IPC分类号： H01L21/336

CPC分类号： H01L21/823878 ,  H01L21/823807 ,  H01L29/665 ,  H01L29/66651 ,  H01L29/7843

摘要： A method of manufacturing a metal-oxide-semiconductor transistor device is disclosed, in which, an insulation region is formed to define the insulation region and an active region, wherein the active region is adjacent to the insulation region and electrically insulated by the insulation region. A selective epitaxial process is performed to form an epitaxial layer on the active region; wherein the epitaxial layer laterally extends onto a surface of a peripheral portion of the insulation region. Thereafter, a doped well is formed in the semiconductor substrate of the active region. A gate structure is formed on the epitaxial layer. Finally, a drain/source region is formed in the semiconductor substrate and the epitaxial layer at a side of the gate structure.

摘要翻译： 公开了一种制造金属氧化物半导体晶体管器件的方法，其中形成绝缘区域以限定绝缘区域和有源区域，其中有源区域与绝缘区域相邻并且被绝缘区域电绝缘 。 执行选择性外延工艺以在有源区上形成外延层; 其中所述外延层横向延伸到所述绝缘区域的周边部分的表面上。 此后，在有源区的半导体衬底中形成掺杂阱。 栅极结构形成在外延层上。 最后，半导体衬底和栅极结构侧的外延层形成漏极/源极区。

公开(公告)号：US06855376B2

公开(公告)日：2005-02-15

申请号：US10237695

申请日：2002-09-10

申请人： Chien-Liang Hwang ,  Jack Ting ,  Jih-Shun Chiang ,  Chuan Chuang

发明人： Chien-Liang Hwang ,  Jack Ting ,  Jih-Shun Chiang ,  Chuan Chuang

IPC分类号： B82B3/00 ,  C01B31/02 ,  C23C14/14 ,  C23C16/02 ,  C23C16/26 ,  C30B25/00 ,  H01J9/02 ,  B05D1/36 ,  C23D8/00 ,  C23C16/00 ,  C23C28/00 ,  C25D5/12

CPC分类号： C23C16/0281 ,  B82Y30/00 ,  C23C16/26 ,  C23C28/021 ,  C23C28/023 ,  C30B25/00 ,  C30B29/605 ,  Y10S977/843 ,  Y10S977/89

摘要： Carbon nanotubes are directly grown on a substrate surface having three metal layers thereon by a thermal chemical vapor deposition at low-temperature, which can be used as an electron emission source for field emission displays. The three layers include a layer of an active metal catalyst sandwiched between a thick metal support layer formed on the substrate and a bonding metal layer. The active metal catalyst is iron, cobalt, nickel or an alloy thereof; the metal support and the bonding metal independently are Au, Ag, Cu, Pd, Pt or an alloy thereof; and they can be formed by sputtering, chemical vapor deposition, physical vapor deposition, screen printing or electroplating.

摘要翻译： 碳纳米管通过在低温下的热化学气相沉积在其上具有三个金属层的基板表面上直接生长，这可以用作场发射显示器的电子发射源。 三层包括夹在形成在基板上的厚金属支撑层和接合金属层之间的活性金属催化剂层。 活性金属催化剂是铁，钴，镍或其合金; 金属载体和键合金属独立地为Au，Ag，Cu，Pd，Pt或其合金; 它们可以通过溅射，化学气相沉积，物理气相沉积，丝网印刷或电镀形成。

公开(公告)号：US20080293222A1

公开(公告)日：2008-11-27

申请号：US12179576

申请日：2008-07-24

申请人： Jih-Shun Chiang ,  Hung-Lin Shih ,  Li-Yuen Tang ,  Tian-Fu Chiang ,  Ming-Chi Fan ,  Chin-I Liao ,  Chin-Cheng Chien

发明人： Jih-Shun Chiang ,  Hung-Lin Shih ,  Li-Yuen Tang ,  Tian-Fu Chiang ,  Ming-Chi Fan ,  Chin-I Liao ,  Chin-Cheng Chien

IPC分类号： H01L21/205

CPC分类号： H01L29/66636 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L29/6656 ,  H01L29/66628

摘要： A method for forming a SiGe epitaxial layer is described. A first SEG process is performed under a first condition, consuming about 1% to 20% of the total process time for forming the SiGe epitaxial layer. Then, a second SEG process is performed under a second condition, consuming about 99% to 80% of the total process time. The first condition and the second condition include different temperatures or pressures. The first and the second SEG processes each uses a reactant gas that includes at least a Si-containing gas and a Ge-containing gas.

摘要翻译： 描述了形成SiGe外延层的方法。 在第一条件下执行第一SEG工艺，消耗用于形成SiGe外延层的总工艺时间的约1％至20％。 然后，在第二条件下执行第二SEG处理，消耗总处理时间的约99％至80％。 第一个条件和第二个条件包括不同的温度或压力。 第一和第二SEG方法各自使用至少包含含Si气体和含Ge气体的反应气体。

公开(公告)号：US20080076236A1

公开(公告)日：2008-03-27

申请号：US11309739

申请日：2006-09-21

申请人： Jih-Shun Chiang ,  Hung-Lin Shih ,  Li-Yuen Tang ,  Tian-Fu Chiang ,  Ming-Chi Fan ,  Chin-I Liao ,  Chin-Cheng Chien

发明人： Jih-Shun Chiang ,  Hung-Lin Shih ,  Li-Yuen Tang ,  Tian-Fu Chiang ,  Ming-Chi Fan ,  Chin-I Liao ,  Chin-Cheng Chien

IPC分类号： H01L21/20 ,  H01L33/00 ,  H01L21/36

CPC分类号： H01L29/66636 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L29/6656 ,  H01L29/66628

摘要： A method for forming a SiGe epitaxial layer is described. A first SEG process is performed under a first condition, consuming about 1% to 20% of the total process time for forming the SiGe epitaxial layer. Then, a second SEG process is performed under a second condition, consuming about 99% to 80% of the total process time. The first condition and the second condition include different temperatures or pressures. The first and the second SEG processes each uses a reactant gas that includes at least a Si-containing gas and a Ge-containing gas.

公开(公告)号：US06821911B1

公开(公告)日：2004-11-23

申请号：US10727500

申请日：2003-12-05

申请人： Po-Yuan Lo ,  Jih-Shun Chiang ,  Jeng-Hua Wei ,  Chien-Liang Hwang ,  Hung-Hsiang Wang ,  Ming-Jiunn Lai ,  Ming-Jer Kao

发明人： Po-Yuan Lo ,  Jih-Shun Chiang ,  Jeng-Hua Wei ,  Chien-Liang Hwang ,  Hung-Hsiang Wang ,  Ming-Jiunn Lai ,  Ming-Jer Kao

IPC分类号： H01L21649

CPC分类号： H01L51/0545 ,  B82Y10/00 ,  H01L51/0048 ,  Y10S977/75 ,  Y10S977/843 ,  Y10S977/888

摘要： A manufacturing method of carbon nanotube transistors is disclosed. The steps include: forming an insulating layer on a substrate; forming a first oxide layer on the insulating layer using a solution with cobalt ion catalyst by spin-on-glass (SOG); forming a second oxide layer on the first oxide layer using a solution without the catalyst; forming a blind hole on the second oxide layer using photolithographic and etching processes, the blind hole exposing the first oxide layer, the sidewall of the second oxide layer, and the insulating layer; forming a single wall carbon nanotube (SWNT) connecting the first oxide layer separated by the blind hole and parallel to the substrate; and forming a source and a drain connecting to both ends of the SWNT, respectively.

摘要翻译： 公开了一种碳纳米管晶体管的制造方法。 所述步骤包括：在基板上形成绝缘层; 使用通过旋涂玻璃（SOG）的钴离子催化剂的溶液在绝缘层上形成第一氧化物层; 使用不含催化剂的溶液在所述第一氧化物层上形成第二氧化物层; 使用光刻和蚀刻工艺在第二氧化物层上形成盲孔，盲孔暴露第一氧化物层，第二氧化物层的侧壁和绝缘层; 形成连接由盲孔分离并平行于基板的第一氧化物层的单壁碳纳米管（SWNT）; 并且分别形成连接到SWNT的两端的源极和漏极。

公开(公告)号：US20080061366A1

公开(公告)日：2008-03-13

申请号：US11530480

申请日：2006-09-11

申请人： Che-Hung Liu ,  Po-Lun Cheng ,  Chun-An Lin ,  Li-Yuen Tang ,  Hung-Lin Shih ,  Ming-Chi Fan ,  Hsien-Liang Meng ,  Jih-Shun Chiang

发明人： Che-Hung Liu ,  Po-Lun Cheng ,  Chun-An Lin ,  Li-Yuen Tang ,  Hung-Lin Shih ,  Ming-Chi Fan ,  Hsien-Liang Meng ,  Jih-Shun Chiang

IPC分类号： H01L29/76

CPC分类号： H01L29/7843 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7834

摘要： A complementary metal-oxide-semiconductor (CMOS) device includes a substrate with a first active region and a second active region; a first gate structure and a second gate structure, respectively disposed on the first active region and the second active region; a first spacer structure and a second spacer structure respectively disposed on sidewalls of the first gate structure and the second gate structure; a first LDD and a second LDD respectively disposed in the substrate at both sides of the first gate structure and the second gate structure; an epitaxial material layer, disposed in the first active region and located on a side of the first LDD; and a passivation layer, disposed on the first gate structure, the first spacer structure, and the first LDD and covering the second active region, wherein the passivation layer comprises a carbon-containing oxynitride layer.

摘要翻译： 互补金属氧化物半导体（CMOS）器件包括具有第一有源区和第二有源区的衬底; 分别设置在所述第一有源区和所述第二有源区上的第一栅极结构和第二栅极结构; 分别设置在第一栅极结构和第二栅极结构的侧壁上的第一间隔结构和第二间隔结构; 在第一栅极结构和第二栅极结构的两侧分别设置在基板中的第一LDD和第二LDD; 外延材料层，设置在第一有源区并位于第一LDD的一侧; 以及钝化层，设置在所述第一栅极结构上，所述第一间隔结构和所述第一LDD并且覆盖所述第二有源区，其中所述钝化层包含含碳氮氧化物层。

公开(公告)号：US20080017931A1

公开(公告)日：2008-01-24

申请号：US11458393

申请日：2006-07-19

申请人： Hung-Lin Shih ,  Jih-Shun Chiang ,  Hsien-Liang Meng

发明人： Hung-Lin Shih ,  Jih-Shun Chiang ,  Hsien-Liang Meng

IPC分类号： H01L29/76 ,  H01L21/8238

CPC分类号： H01L21/823878 ,  H01L21/823807 ,  H01L29/665 ,  H01L29/66651 ,  H01L29/7843

摘要： A metal-oxide-semiconductor transistor device comprises a semiconductor substrate comprising an active region and an insulation region, a selective epitaxial layer between the active region and a gate structure, wherein a peripheral portion of the epitaxial layer is over a peripheral portion of the insulation region, such that the width of the channel is increased and a drain current is improved.

摘要翻译： 金属氧化物半导体晶体管器件包括半导体衬底，其包括有源区和绝缘区，在有源区和栅极结构之间的选择性外延层，其中外延层的周边部分在绝缘体的周边部分之上 使得通道的宽度增加并且提高漏极电流。

公开(公告)号：US07226531B2

公开(公告)日：2007-06-05

申请号：US11298523

申请日：2005-12-12

申请人： Po-Yuan Lo ,  Jung-Hua Wei ,  Bae-Horng Chen ,  Jih-Shun Chiang ,  Chian-Liang Hwang ,  Ming-Jer Kao

发明人： Po-Yuan Lo ,  Jung-Hua Wei ,  Bae-Horng Chen ,  Jih-Shun Chiang ,  Chian-Liang Hwang ,  Ming-Jer Kao

IPC分类号： C25D5/02 ,  C25D5/56

CPC分类号： C25D5/02 ,  C25D3/38 ,  C25D5/54

摘要： Method of making an electroplated interconnection wire of a composite of metal and carbon nanotubes is disclosed, including electroplating a substrate having a conductive baseline on a surface thereof in an electroplating bath containing a metal ion and carbon nanotubes, so that an electroplated interconnection wire of a composite of the metal and carbon nanotubes is formed on the conductive baseline. Alternatively, a method of the present invention includes preparing a dispersion of carbon nanotubes dispersed in an organic solvent, printing a baseline with the dispersion on a surface of a substrate, evaporating the organic solvent to obtain a conductive baseline, and electroplating the surface in an electroplating bath containing a metal ion, so that an electroplated interconnection wire of a composite of the metal and carbon nanotubes is formed on the conductive baseline.

公开(公告)号：US07402496B2

公开(公告)日：2008-07-22

申请号：US11530480

申请日：2006-09-11

申请人： Che-Hung Liu ,  Po-Lun Cheng ,  Chun-An Lin ,  Li-Yuen Tang ,  Hung-Lin Shih ,  Ming-Chi Fan ,  Hsien-Liang Meng ,  Jih-Shun Chiang

发明人： Che-Hung Liu ,  Po-Lun Cheng ,  Chun-An Lin ,  Li-Yuen Tang ,  Hung-Lin Shih ,  Ming-Chi Fan ,  Hsien-Liang Meng ,  Jih-Shun Chiang

IPC分类号： H01L21/336

CPC分类号： H01L29/7843 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7834

摘要： A complementary metal-oxide-semiconductor (CMOS) device includes a substrate with a first active region and a second active region; a first gate structure and a second gate structure, respectively disposed on the first active region and the second active region; a first spacer structure and a second spacer structure respectively disposed on sidewalls of the first gate structure and the second gate structure; a first LDD and a second LDD respectively disposed in the substrate at both sides of the first gate structure and the second gate structure; an epitaxial material layer, disposed in the first active region and located on a side of the first LDD; and a passivation layer, disposed on the first gate structure, the first spacer structure, and the first LDD and covering the second active region, wherein the passivation layer comprises a carbon-containing oxynitride layer.

摘要翻译： 互补金属氧化物半导体（CMOS）器件包括具有第一有源区和第二有源区的衬底; 分别设置在所述第一有源区和所述第二有源区上的第一栅极结构和第二栅极结构; 分别设置在第一栅极结构和第二栅极结构的侧壁上的第一间隔结构和第二间隔结构; 在第一栅极结构和第二栅极结构的两侧分别设置在基板中的第一LDD和第二LDD; 外延材料层，设置在第一有源区并位于第一LDD的一侧; 以及钝化层，设置在所述第一栅极结构上，所述第一间隔结构和所述第一LDD并且覆盖所述第二有源区，其中所述钝化层包含含碳氮氧化物层。