公开(公告)号：US20120166130A1

公开(公告)日：2012-06-28

申请号：US12979914

申请日：2010-12-28

申请人： Yun-Chi YANG ,  Yen-Song Liu ,  Chin-Hsien Chen ,  Sheng-Yu Wu ,  Kuan-Cheng Su

发明人： Yun-Chi YANG ,  Yen-Song Liu ,  Chin-Hsien Chen ,  Sheng-Yu Wu ,  Kuan-Cheng Su

IPC分类号： G06F19/00

CPC分类号： G11C29/52 ,  G01R31/287 ,  G11C29/42 ,  G11C29/44 ,  G11C29/56008 ,  G11C2029/0409 ,  G11C2029/0411

摘要： A method for evaluating failure rate, which is applied to a plurality of semiconductor chips with error checking and correcting function includes the following steps. A first read-write test operation is applied to the semiconductor chips, thereby obtaining a plurality of first failure bit counting values. The error checking and correcting function of each of the semiconductor chips is off. An aging test is applied to the semiconductor chips. A second read-write test operation as the first read-write test operation is applied to the semiconductor chips, thereby obtaining a plurality of second failure bit counting values. The number of the semiconductor chips, the first failure bit counting values, the second failure bit counting values and an error checking and correcting coefficient are calculated to obtain a failure rate of the semiconductor chips.

摘要翻译： 一种用于评估故障率的方法，其应用于具有错误检查和校正功能的多个半导体芯片包括以下步骤。 对半导体芯片应用第一读写测试操作，从而获得多个第一故障比特计数值。 每个半导体芯片的错误检查和校正功能关闭。 对半导体芯片进行老化试验。 作为第一读写测试操作的第二读写测试操作被应用于半导体芯片，从而获得多个第二故障位计数值。 计算半导体芯片的数量，第一故障比特计数值，第二故障比特计数值和错误校验系数，以获得半导体芯片的故障率。

公开(公告)号：US08510635B2

公开(公告)日：2013-08-13

申请号：US12979914

申请日：2010-12-28

申请人： Yun-Chi Yang ,  Yen-Song Liu ,  Chin-Hsien Chen ,  Sheng-Yu Wu ,  Kuan-Cheng Su

发明人： Yun-Chi Yang ,  Yen-Song Liu ,  Chin-Hsien Chen ,  Sheng-Yu Wu ,  Kuan-Cheng Su

IPC分类号： G11C29/00

CPC分类号： G11C29/52 ,  G01R31/287 ,  G11C29/42 ,  G11C29/44 ,  G11C29/56008 ,  G11C2029/0409 ,  G11C2029/0411

摘要： A method for evaluating failure rate, which is applied to a plurality of semiconductor chips with error checking and correcting function includes the following steps. A first read-write test operation is applied to the semiconductor chips, thereby obtaining a plurality of first failure bit counting values. The error checking and correcting function of each of the semiconductor chips is off. An aging test is applied to the semiconductor chips. A second read-write test operation as the first read-write test operation is applied to the semiconductor chips, thereby obtaining a plurality of second failure bit counting values. The number of the semiconductor chips, the first failure bit counting values, the second failure bit counting values and an error checking and correcting coefficient are calculated to obtain a failure rate of the semiconductor chips.

摘要翻译： 一种用于评估故障率的方法，其应用于具有错误检查和校正功能的多个半导体芯片包括以下步骤。 对半导体芯片应用第一读写测试操作，从而获得多个第一故障比特计数值。 每个半导体芯片的错误检查和校正功能关闭。 对半导体芯片进行老化试验。 作为第一读写测试操作的第二读写测试操作被应用于半导体芯片，从而获得多个第二故障位计数值。 计算半导体芯片的数量，第一故障比特计数值，第二故障比特计数值和错误校验系数，以获得半导体芯片的故障率。

公开(公告)号：US07589551B1

公开(公告)日：2009-09-15

申请号：US12107772

申请日：2008-04-23

申请人： Yun-Chi Yang ,  Chao-Yung Lai ,  Chao-Yang Lin ,  Cheng-Li Lin ,  Kuan-Cheng Su

发明人： Yun-Chi Yang ,  Chao-Yung Lai ,  Chao-Yang Lin ,  Cheng-Li Lin ,  Kuan-Cheng Su

IPC分类号： G01R31/26 ,  G01R31/02

CPC分类号： G01R31/2858 ,  G01R31/2884

摘要： To make an alternating current (AC) stress test easier to perform in a wafer, an AC stress test circuit for performing the AC stress test on a test device fabricated in a test region of the wafer includes an oscillator module fabricated in the test region, a diode module fabricated in the test region coupled to an output of the oscillator module, and a select transistor fabricated in the test region having a gate terminal coupled to an output of the diode module, a second terminal coupled to a gate of the test device, and a third terminal coupled to a test voltage source.

摘要翻译： 为了在晶片中更容易进行交流（AC）应力测试，用于对在晶片的测试区域中制造的测试装置进行AC应力测试的AC应力测试电路包括在测试区域中制造的振荡器模块， 制造在耦合到振荡器模块的输出的测试区域中的二极管模块，以及制造在测试区域中的选择晶体管，其具有耦合到二极管模块的输出的栅极端子，耦合到测试装置的栅极的第二端子 以及耦合到测试电压源的第三端子。

公开(公告)号：US20080270056A1

公开(公告)日：2008-10-30

申请号：US11740916

申请日：2007-04-26

申请人： Yun-Chi Yang ,  Cheng-Li Lin ,  Chia-Jen Kao ,  Ju-Ping Chen ,  Kuan-Cheng Su

发明人： Yun-Chi Yang ,  Cheng-Li Lin ,  Chia-Jen Kao ,  Ju-Ping Chen ,  Kuan-Cheng Su

IPC分类号： H01L21/66 ,  G01N37/00

CPC分类号： H01L22/20

摘要： A yield enhancement system has a fabrication line with semiconductor fabrication devices for fabricating a wafer, an inspection and measurement monitoring system coupled to the fabrication line for determining process data corresponding to semiconductor fabrication devices, and a post-process testing line coupled to the fabrication line for performing in-line wafer-level testing. The post-process testing line includes a wafer acceptance tester, a yield monitor coupled to the wafer acceptance tester, and a wafer level reliability tester coupled to the wafer acceptance tester for estimating a life span of a device on the wafer.

摘要翻译： 屈服增强系统具有制造线，其具有用于制造晶片的半导体制造装置，耦合到制造线的检查和测量监测系统，用于确定对应于半导体制造装置的工艺数据，以及耦合到制造线的后处理测试线 用于进行在线晶圆级测试。 后处理测试线包括晶片接收测试仪，耦合到晶片接收测试仪的屈服监测器，以及耦合到晶片接收测试仪的晶片级可靠性测试器，用于估计晶片上的器件的寿命。

公开(公告)号：US20090278170A1

公开(公告)日：2009-11-12

申请号：US12116231

申请日：2008-05-07

申请人： Yun-Chi Yang ,  Jih-Shun Chiang ,  Cheng-Li Lin ,  Ju-Ping Chen ,  Kuan-Cheng Su

发明人： Yun-Chi Yang ,  Jih-Shun Chiang ,  Cheng-Li Lin ,  Ju-Ping Chen ,  Kuan-Cheng Su

IPC分类号： H01L29/778 ,  H01L21/336

CPC分类号： H01L29/66636 ,  H01L21/28518 ,  H01L21/3148 ,  H01L29/456 ,  H01L29/665

摘要： A method for manufacturing a semiconductor device includes providing a substrate having at least a gate structure formed thereon, forming LDDs in the substrate respectively at two side of the gate structure and a spacer at sidewalls of the gate structure, forming a source/drain in the substrate at two side of the gate structure, performing ant etching process to form recesses respectively in the source/drain, forming a barrier layer in the recesses; and performing a salicide process.

摘要翻译： 一种制造半导体器件的方法包括提供至少形成有栅极结构的衬底，分别在栅极结构的两侧在衬底中形成LDD，在栅极结构的侧壁形成间隔物，在栅极结构的侧壁形成源极/漏极 基板在栅极结构的两侧，进行蚂蚁蚀刻处理以分别在源极/漏极中形成凹槽，在凹部中形成阻挡层; 并执行自杀过程。

公开(公告)号：US08648421B2

公开(公告)日：2014-02-11

申请号：US13290399

申请日：2011-11-07

申请人： Yung-Ju Wen ,  Chang-Tzu Wang ,  Tien-Hao Tang ,  Kuan-Cheng Su

发明人： Yung-Ju Wen ,  Chang-Tzu Wang ,  Tien-Hao Tang ,  Kuan-Cheng Su

IPC分类号： H01L23/60

CPC分类号： H01L29/78 ,  H01L27/0266 ,  H01L29/41758 ,  H01L29/4966

摘要： An electrostatic discharge (ESD) device is described, including a gate line, a source region at a first side of the gate line, a comb-shaped drain region disposed at a second side of the gate line and having comb-teeth parts, a salicide layer on the source region and the drain region, and contact plugs on the salicide layer on the source region and the drain region. Each comb-teeth part has thereon, at a tip portion thereof, at least one of the contact plugs.

摘要翻译： 描述了静电放电（ESD）器件，包括栅极线，栅极线第一侧的源极区域，设置在栅极线的第二侧并具有梳齿部分的梳状漏极区域， 源极区域和漏极区域上的自对准硅化物层，以及源极区域和漏极区域上的自对准硅化物层上的接触塞。 每个梳齿部分在其顶端部分上具有至少一个接触塞。

公开(公告)号：US06171899B2

公开(公告)日：2001-01-09

申请号：US09267535

申请日：1999-03-12

申请人： Fu-Tai Liou ,  Water Lur ,  Kuan-Cheng Su ,  Juan-Yuan Wu

发明人： Fu-Tai Liou ,  Water Lur ,  Kuan-Cheng Su ,  Juan-Yuan Wu

IPC分类号： H01L218242

CPC分类号： H01L28/60 ,  H01L21/76838

摘要： A method for fabricating a capacitor. A first metal layer is formed on a provided substrate. A dielectric film is formed on the first metal layer. The dielectric film can be a mono-layer structure or a multi-layer structure comprising various dielectric materials. A rapid thermal process (RTP), such as a rapid thermal annealing, or a plasma treatment is performed to enhance the quality of the dielectric film. A photolithography and etching process is performed to remove a part of the dielectric film and the first metal layer to expose a part of the inter-layer dielectric layer. The remaining first conductive layer is used as a lower electrode. A conventional interconnect process is performed on the exposed inter-layer dielectric layer and on the dielectric film. For example, a glue layer is formed on the exposed inter-layer dielectric layer and on the dielectric film. A second metal layer is formed on the glue layer. A photolithography and etching process is performed to remove a part of the second conductive layer. The second metal layer remaining on the inter-layer dielectric layer is used as a wiring line for interconnection. The glue layer remaining on the dielectric film is used as an upper electrode.

摘要翻译： 一种制造电容器的方法。 在所提供的基板上形成第一金属层。 在第一金属层上形成电介质膜。 电介质膜可以是单层结构或包括各种介电材料的多层结构。 进行快速热处理（RTP），例如快速热退火或等离子体处理，以提高电介质膜的质量。 进行光刻和蚀刻处理以去除电介质膜和第一金属层的一部分以暴露层间电介质层的一部分。 剩余的第一导电层用作下电极。 在暴露的层间电介质层和电介质膜上进行常规的互连工艺。 例如，在暴露的层间电介质层和电介质膜上形成胶层。 第二金属层形成在胶层上。 执行光刻和蚀刻工艺以去除第二导电层的一部分。 残留在层间电介质层上的第二金属层用作互连布线。 残留在电介质膜上的胶层用作上电极。

公开(公告)号：US5665995A

公开(公告)日：1997-09-09

申请号：US429603

申请日：1995-04-27

申请人： Chen-Chiu Hsue ,  Shing-Ren Shev ,  Kuan-Cheng Su ,  Chen-Hui Chung

发明人： Chen-Chiu Hsue ,  Shing-Ren Shev ,  Kuan-Cheng Su ,  Chen-Hui Chung

IPC分类号： H01L21/8246 ,  H01L27/112 ,  H01L29/76

CPC分类号： H01L27/1126 ,  H01L27/112

摘要： A ROM device with an array of cells has conductors formed in a substrate. Insulation is formed, and parallel conductors are formed orthogonally to the line regions, as thin as about 2000 .ANG.. Glass insulation having a thickness of about 3000 .ANG. or less, formed over the conductors is is reflowed. Contacts and a metal layer on the glass insulation are formed. Resist is patterned and used for etching the resist pattern in the metal. Removal of the second resist and device passivation with a layer having a thickness of about 1000 .ANG., precede activation of the impurity ions by annealing the device at less than or equal to about 520.degree. C. in a reducing gas atmosphere. After resist removal, a second resist is formed and exposed with a custom code pattern to form a mask. Ions are implanted into the substrate with a dosage of between about 1 E 14 and 3 E 14 atoms/cm.sup.2 with an energy of less than or equal to 200 keV adjacent to the conductors through the openings in the insulation.

摘要翻译： 具有单元阵列的ROM器件具有形成在衬底中的导体。 形成绝缘体，平行导体与线区域正交形成，薄至约2000安。 在导体上形成厚度约为3000或更小的玻璃绝缘体被回流。 形成玻璃绝缘体上的触点和金属层。 抗蚀剂被图案化并用于蚀刻金属中的抗蚀剂图案。 在还原气体气氛中，通过在小于或等于约520℃退火器件使杂质离子激活之前，用厚度约为1000的层去除第二抗蚀剂和器件钝化。 抗蚀剂除去后，形成第二抗蚀剂并用定制的编码图案曝光以形成掩模。 离子以约1E14和3E14原子/ cm2的剂量注入到基底中，其能量小于或等于200keV，通过绝缘体中的开口与导体相邻。

公开(公告)号：US5576573A

公开(公告)日：1996-11-19

申请号：US454701

申请日：1995-05-31

申请人： Kuan-Cheng Su ,  Shing-Ren Sheu

发明人： Kuan-Cheng Su ,  Shing-Ren Sheu

IPC分类号： H01L27/112 ,  H01L29/423 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC分类号： H01L27/112 ,  H01L29/42368 ,  Y10S438/981

摘要： A multi-state memory cell for a mask ROM device. Source/drain regions are arranged on a substrate as strips extending along a first direction on the plane of the substrate and bit lines. Gate oxide layers are arranged on the substrate as strips extending along a second direction. Gate electrodes are each formed on top of each of the gate oxide layers as strips extending along the second direction. The gate oxide layers have a number of selected thickness' arranged in a differential series. Each of the transistor channel regions, together with their corresponding one of the neighboring source/drain pair, the gate oxide layer on top, and the gate electrodes further on top thereof constitute one of the memory cells that can have its threshold voltage varied among the differential series of thicknesses allowing for the storage of a multi-bit equivalent of memory content for the memory cell.

摘要翻译： 一种用于掩模ROM器件的多状态存储单元。 源极/漏极区域沿着衬底和位线的平面上沿着第一方向延伸的条带布置在衬底上。 栅极氧化物层沿着第二方向布置在基板上。 栅极电极分别形成在每个栅极氧化物层的顶部上，作为沿第二方向延伸的条带。 栅极氧化物层具有多个选定的厚度，以差分系列排列。 每个晶体管沟道区以及它们相应的一个源极/漏极对，顶部的栅极氧化物层和进一步在其顶部的栅电极构成一个存储单元，其可以使其阈值电压在 差分系列的厚度允许存储用于存储器单元的多位等效的存储器内容。

公开(公告)号：US5504030A

公开(公告)日：1996-04-02

申请号：US505050

申请日：1995-07-21

申请人： Chen-Hui Chung ,  Kuan-Cheng Su ,  Yi-Chung Sheng

发明人： Chen-Hui Chung ,  Kuan-Cheng Su ,  Yi-Chung Sheng

IPC分类号： H01L21/8246

CPC分类号： H01L27/11246 ,  Y10S438/981

摘要： A method of fabricating memory cells of a mask ROM device. A plurality of source/drain regions extending along a first direction is formed by implanting impurities into a semiconductor substrate, constituting bit lines of the memory cells. A code oxide layer is formed on a designated area of the semiconductor substrate defined by a barrier layer using a liquid-phase deposition process, whereby a multi-state mask ROM is fabricated by repeatedly performing the liquid-phase deposition process to form a series of coding oxide layers having increasing thicknesses. A gate oxide layer is formed on a portion of the semiconductor substrate not covered by the coding oxide layers. The thickness of the gate oxide layer is smaller than that of the coding oxide layers. A plurality of gate electrodes extending along a second direction orthogonal to the first direction is formed by depositing and patterning a conducting layer on the coding oxide layer and the gate oxide layer, constituting word lines of said memory cells. The cross area of every two adjacent bit lines and one word line thereby forms a memory cell of the mask ROM wherein threshold voltages of the memory cells are altered proportional to the thicknesses of the gate oxide layer and the coding oxide layers.

摘要翻译： 一种制造掩模ROM器件的存储单元的方法。 沿着第一方向延伸的多个源极/漏极区域通过将杂质注入构成存储器单元的位线的半导体衬底中而形成。 在通过液相沉积工艺由阻挡层限定的半导体衬底的指定区域上形成编码氧化物层，由此通过反复进行液相沉积工艺以形成一系列 编码具有增加的厚度的氧化物层。 在不被编码氧化物层覆盖的半导体衬底的一部分上形成栅氧化层。 栅极氧化物层的厚度小于编码氧化物层的厚度。 通过在构成所述存储单元的字线的编码氧化物层和栅极氧化物层上沉积和图案化导电层来形成沿着与第一方向正交的第二方向延伸的多个栅电极。 因此，每两个相邻位线和一个字线的横截面形成掩模ROM的存储单元，其中存储单元的阈值电压与栅极氧化物层和编码氧化物层的厚度成比例地变化。