公开(公告)号：US20050083620A1

公开(公告)日：2005-04-21

申请号：US10710093

申请日：2004-06-18

申请人： Yung-Hao Lin ,  Tay-Her Tsaur ,  Ta-Hsun Yeh ,  Chao-Cheng Lee

发明人： Yung-Hao Lin ,  Tay-Her Tsaur ,  Ta-Hsun Yeh ,  Chao-Cheng Lee

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L23/60 ,  H01L27/02 ,  H01L27/06 ,  H02H9/00

CPC分类号： H01L27/0266

摘要： An ESD protection circuit installed among a plurality of reference nodes includes a clamping device coupled between two reference nodes among the plurality of reference nodes; a stack-coupling device coupled between the clamping device and one of the reference nodes; and at least a resistive device coupled between the stack-coupling device and another one of the reference nodes.

摘要翻译： 安装在多个参考节点之间的ESD保护电路包括耦合在多个参考节点中的两个参考节点之间的夹紧装置; 耦合在所述夹持装置和所述参考节点之一之间的叠层耦合装置; 以及耦合在所述堆叠耦合装置与所述参考节点中的另一个之间的至少一个电阻装置。

公开(公告)号：US06940104B2

公开(公告)日：2005-09-06

申请号：US10844455

申请日：2004-05-13

申请人： Ta-Hsun Yeh ,  Chao-Cheng Lee ,  Tay-Her Tsaur

发明人： Ta-Hsun Yeh ,  Chao-Cheng Lee ,  Tay-Her Tsaur

IPC分类号： H01L27/02 ,  H01L27/08 ,  H01L29/861 ,  H01L29/88

CPC分类号： H01L27/0814 ,  H01L27/0255 ,  H01L2924/0002 ,  H01L2924/00

摘要： A cascaded diode structure with a deep N-well for effectively reducing the leakage current of the P-type substrate by floating the base of a parasitic transistor in the cascaded diode structure. The cascaded diode structure includes a P-type substrate, a deep N-well formed on the P-type substrate, a plurality of elemental diodes formed on the deep N-well, and a plurality of connecting parts for cascading the elemental diodes. Each elemental diode includes a P-well formed on the deep N-well, a heavily doped P-type region formed on the P-well, and a heavily doped N-type region formed on the P-well.

公开(公告)号：US20050012156A1

公开(公告)日：2005-01-20

申请号：US10844455

申请日：2004-05-13

申请人： Ta-Hsun Yeh ,  Chao-Cheng Lee ,  Tay-Her Tsaur

发明人： Ta-Hsun Yeh ,  Chao-Cheng Lee ,  Tay-Her Tsaur

IPC分类号： H01L27/02 ,  H01L27/08 ,  H01L29/76

CPC分类号： H01L27/0814 ,  H01L27/0255 ,  H01L2924/0002 ,  H01L2924/00

摘要： A cascaded diode structure with a deep N-well for effectively reducing the leakage current of the P-type substrate by floating the base of a parasitic transistor in the cascaded diode structure. The cascaded diode structure includes a P-type substrate, a deep N-well formed on the P-type substrate, a plurality of elemental diodes formed on the deep N-well, and a plurality of connecting parts for cascading the elemental diodes. Each elemental diode includes a P-well formed on the deep N-well, a heavily doped P-type region formed on the P-well, and a heavily doped N-type region formed on the P-well.

摘要翻译： 具有深N阱的级联二极管结构，用于通过浮置级联二极管结构中的寄生晶体管的基极来有效地减少P型衬底的漏电流。 级联二极管结构包括P型衬底，在P型衬底上形成的深N阱，形成在深N阱上的多个元件二极管和用于级联元件二极管的多个连接部件。 每个元件二极管包括形成在深N阱上的P阱，形成在P阱上的重掺杂P型区域和形成在P阱上的重掺杂N型区域。

公开(公告)号：US20050002139A1

公开(公告)日：2005-01-06

申请号：US10868954

申请日：2004-06-17

申请人： Ta-Hsun Yeh ,  Chao-Cheng Lee ,  Tay-Her Tsaur

发明人： Ta-Hsun Yeh ,  Chao-Cheng Lee ,  Tay-Her Tsaur

IPC分类号： H01L23/60 ,  H01L27/02 ,  H01L27/082 ,  H02H9/08

CPC分类号： H01L27/0259 ,  H01L2924/0002 ,  H01L2924/00

摘要： An ESD clamp circuit includes an ESD detecting unit and a discharge circuit with a longitudinal BJT. The longitudinal BJT is formed on a P-type substrate and includes a deep N-well formed on the P-type substrate, a P-well formed on parts of the deep N-well, a N-well formed on the deep N-well surrounding the P-well, a first N+ region formed on parts of the P-well and electrically coupled to a first voltage, a P+ region formed on the P-well surrounding the first N+ region and electrically coupled to a trigger signal, and a second N+ region formed on the N-well and electrically coupled to a second voltage. In the structure of the longitudinal BJT, the leakage current can be decreased, the current gain can be increased, and the dimension of the ESD clamp circuit can be reduced.

摘要翻译： ESD钳位电路包括ESD检测单元和具有纵向BJT的放电电路。 纵向BJT形成在P型衬底上，并且包括在P型衬底上形成的深N阱，在深N阱的一部分上形成的P阱，在深N极上形成的N阱， 环绕P阱，形成在P阱的部分上并电耦合到第一电压的第一N +区，形成在围绕第一N +区并且电耦合到触发信号的P阱上的P +区，以及 形成在N阱上并电耦合到第二电压的第二N +区。 在纵向BJT的结构中，可以减小漏电流，增加电流增益，可以减小ESD钳位电路的尺寸。

公开(公告)号：US20050083623A1

公开(公告)日：2005-04-21

申请号：US10964392

申请日：2004-10-13

申请人： Ta-Hsun Yeh ,  Yung-Hao Lin ,  Yuh-Sheng Jean

发明人： Ta-Hsun Yeh ,  Yung-Hao Lin ,  Yuh-Sheng Jean

IPC分类号： H01L29/70 ,  H01L21/33 ,  H01L21/822 ,  H01L27/02 ,  H01L27/04 ,  H02H9/00

CPC分类号： H01L27/0259 ,  H01L2924/0002 ,  H01L2924/00

摘要： An ESD protection circuit for hybrid voltage sources includes a first bipolar transistor set and a second bipolar transistor set, a first detection circuit, and a second detection circuit. The ON/OFF states of the first bipolar transistor set and the second bipolar transistor set are determined by the first and the second detection circuit, and the ON/OFF states function to isolate terminals of the different voltage sources and discharge electrostatic charges injected into one of the terminals.

摘要翻译： 用于混合电压源的ESD保护电路包括第一双极晶体管组和第二双极晶体管组，第一检测电路和第二检测电路。 第一双极晶体管组和第二双极晶体管组的ON / OFF状态由第一和第二检测电路确定，并且ON / OFF状态用于隔离不同电压源的端子和将静电电荷注入一个 的终端。

公开(公告)号：US07245467B2

公开(公告)日：2007-07-17

申请号：US10964392

申请日：2004-10-13

申请人： Ta-Hsun Yeh ,  Yung-Hao Lin ,  Yuh-Sheng Jean

发明人： Ta-Hsun Yeh ,  Yung-Hao Lin ,  Yuh-Sheng Jean

IPC分类号： H02H9/00

CPC分类号： H01L27/0259 ,  H01L2924/0002 ,  H01L2924/00

摘要： An ESD protection circuit for hybrid voltage sources includes a first bipolar transistor set and a second bipolar transistor set, a first detection circuit, and a second detection circuit. The ON/OFF states of the first bipolar transistor set and the second bipolar transistor set are determined by the first and the second detection circuit, and the ON/OFF states function to isolate terminals of the different voltage sources and discharge electrostatic charges injected into one of the terminals.

摘要翻译： 用于混合电压源的ESD保护电路包括第一双极晶体管组和第二双极晶体管组，第一检测电路和第二检测电路。 第一双极晶体管组和第二双极晶体管组的ON / OFF状态由第一和第二检测电路确定，并且ON / OFF状态用于隔离不同电压源的端子和将静电电荷注入一个 的终端。

公开(公告)号：US20120223796A1

公开(公告)日：2012-09-06

申请号：US13372503

申请日：2012-02-14

申请人： Kai-Yi Huang ,  Yuh-Sheng Jean ,  Ta-Hsun Yeh

发明人： Kai-Yi Huang ,  Yuh-Sheng Jean ,  Ta-Hsun Yeh

IPC分类号： H01F29/02

CPC分类号： H01F21/12 ,  H01F2021/125 ,  H01L23/5227 ,  H01L23/645 ,  H01L2924/0002 ,  H01L2924/00

摘要： A variable inductor includes an inductor element and a first inductance adjusting circuit. The first inductance adjusting circuit includes a first open-loop structure and a first switch element. The first switch element is coupled to the first open-loop structure. When the first switch element is in a conducting state, the first open-loop structure and the first switch element forms a first closed-loop to induce a first magnetic flux which alters a magnetic flux from the inductor element in operation.

摘要翻译： 可变电感器包括电感器元件和第一电感调节电路。 第一电感调节电路包括第一开环结构和第一开关元件。 第一开关元件耦合到第一开环结构。 当第一开关元件处于导通状态时，第一开环结构和第一开关元件形成第一闭环以产生在操作中改变来自电感器元件的磁通量的第一磁通量。

公开(公告)号：US07936245B2

公开(公告)日：2011-05-03

申请号：US12773024

申请日：2010-05-04

申请人： Kai-Yi Huang ,  Yuh-Sheng Jean ,  Ta-Hsun Yeh

发明人： Kai-Yi Huang ,  Yuh-Sheng Jean ,  Ta-Hsun Yeh

IPC分类号： H01F5/00

CPC分类号： H01F17/0006

摘要： A stacked structure of a spiral inductor includes a first metal layer, a second metal layer, a first set of vias, and a second set of vias. The first metal layer includes a first segment, a second segment, and a third segment, wherein the layout direction of the third segment is different from the layout direction of the first and second segments. The second metal layer includes a fourth segment, a fifth segment, and a sixth segment connected to the fifth segment, wherein the layout direction of the sixth segment is different from the layout direction of the fourth and fifth segments. The first set of vias connects the first and fourth segments, and they construct a first shunt winding. The second set of vias connects the second and fifth segments, and they construct a second shunt winding. The third and sixth segments construct a crossover region.

摘要翻译： 螺旋电感器的堆叠结构包括第一金属层，第二金属层，第一组通孔和第二组通孔。 第一金属层包括第一段，第二段和第三段，其中第三段的布局方向与第一段和第二段的布局方向不同。 第二金属层包括第四段，第五段和连接到第五段的第六段，其中第六段的布局方向与第四段和第五段的布局方向不同。 第一组通孔连接第一和第四段，并构成第一个分流绕组。 第二组通孔连接第二和第五段，并且它们构成第二分流绕组。 第三和第六段构成交叉区域。

公开(公告)号：US07612645B2

公开(公告)日：2009-11-03

申请号：US11548687

申请日：2006-10-11

申请人： Ta-Hsun Yeh ,  Yuh-Sheng Jean

发明人： Ta-Hsun Yeh ,  Yuh-Sheng Jean

IPC分类号： H01F5/00

CPC分类号： H01F17/0006 ,  H01F27/34 ,  H01L23/5227 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated inductor formed on a substrate comprises a metal layer pattern, a via layer pattern overlapping and electrically connected to the metal layer, and a redistribution layer pattern overlapping and electrically connected to the via layer. The metal layer pattern, the via layer pattern, and the redistribution layer pattern are a coil pattern.

摘要翻译： 形成在基板上的集成电感器包括金属层图案，与金属层重叠并电连接的通孔层图案，以及重叠并电连接到通孔层的再分布层图案。 金属层图案，通孔层图案和再分布层图案是线圈图案。

公开(公告)号：US20080251841A1

公开(公告)日：2008-10-16

申请号：US12056293

申请日：2008-03-27

申请人： Kai-Yi Huang ,  Ta-Hsun Yeh ,  Yuh-Sheng Jean

发明人： Kai-Yi Huang ,  Ta-Hsun Yeh ,  Yuh-Sheng Jean

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/66659

摘要： The structure of the MOS transistor provided in this invention has LDD (lightly doped drain) and halo doped regions removed from the source, the drain or both regions in the substrate for improved linearity range when operated as a voltage-controlled resistor. The removal of the LDD and halo doped regions is performed by simply modifying the standard mask of the MOS process using a logic operation layer with no extra mask required.

摘要翻译： 在本发明中提供的MOS晶体管的结构具有从源极，漏极或衬底中的两个区域去除的LDD（轻掺杂漏极）和卤素掺杂区域，用于当作为压控电阻器工作时提高线性范围。 通过简单地使用没有额外掩模的逻辑运算层来修改MOS工艺的标准掩模来执行LDD和光晕掺杂区的去除。