公开(公告)号：US20090042521A1

公开(公告)日：2009-02-12

申请号：US12188022

申请日：2008-08-07

申请人： Shoji Otaka ,  Yuta Araki ,  Toru Hashimoto

发明人： Shoji Otaka ,  Yuta Araki ,  Toru Hashimoto

IPC分类号： H04B1/04

CPC分类号： H04B1/0475 ,  H03F1/34 ,  H03F3/24 ,  H04B2001/0433

摘要： A radio transmitter including a combiner which combines input I/Q signals with feedback I/Q signals, a power amplifier which amplifies the quadrature modulated signal, a detector which detects amplitude and phase differences between the input and feedback I/Q signals, a switch to turn on and off the feedback I/Q signals, a generator to generate control signals which minimizes the amplitude difference and the phase difference, in a state where a transmission power is set, during for a period during which the switch is turned off, an amplitude adjuster which adjusts an amplitude of the feedback RF signal, during a period during which the switch is turned on, and a phase adjuster which adjusts a phase of the local signal, during the period during which the switch is turned on.

摘要翻译： 一种无线电发射机，包括将输入I / Q信号与反馈I / Q信号组合的组合器，放大正交调制信号的功率放大器，检测输入和反馈I / Q信号之间的幅度和相位差的检测器，开关 打开和关闭反馈I / Q信号的发生器，用于产生控制信号，在发送功率被设定的状态下，在关闭开关的时段期间使幅度差和相位差最小化的控制信号， 幅度调节器，其在开关导通的时段期间调整反馈RF信号的幅度;以及相位调节器，其在开关接通期间调节本地信号的相位。

公开(公告)号：US07663420B2

公开(公告)日：2010-02-16

申请号：US11936214

申请日：2007-11-07

申请人： Yuta Araki ,  Shoji Otaka ,  Toru Hashimoto

发明人： Yuta Araki ,  Shoji Otaka ,  Toru Hashimoto

IPC分类号： H03L5/00

CPC分类号： H01L27/0802 ,  H03H11/245

摘要： A MOS resistance controlling device includes: a plurality of MOS transistors having a first MOS transistor to N-th (the integer N is larger than 1) MOS transistor being serially connected, the source of the first MOS transistor being set to a first reference potential, the drain the N-th MOS transistor being set to a second reference potential, and the drain of an I-th MOS transistor being connected to the source of an I+1-th MOS transistor, where I is an integer from 1 to N−1; a current source which is electrically disposed at connection node between the drain of the N-th MOS transistors and the second reference potential; and an operational amplifier having a first input terminal being supplied with a third reference potential, a second input terminal connected with the connection node and an output terminal being connected with gates of the MOS transistors.

摘要翻译： MOS电阻控制装置包括：多个MOS晶体管，其具有串联连接的第一MOS晶体管至第N（整数N大于1）的MOS晶体管，第一MOS晶体管的源极被设置为第一参考电位 ，第N个MOS晶体管的漏极被设置为第二参考电位，并且第一MOS晶体管的漏极连接到第I + 1个MOS晶体管的源极，其中I是从1到 N-1; 电流源，电流配置在第N个MOS晶体管的漏极与第2基准电位之间的连接节点处; 以及具有被提供有第三参考电位的第一输入端的运算放大器，与所述连接节点连接的第二输入端和与所述MOS晶体管的栅极连接的输出端。

公开(公告)号：US20080311867A1

公开(公告)日：2008-12-18

申请号：US12025314

申请日：2008-02-04

申请人： Yuta Araki ,  Shoji Otaka ,  Toru Hashimoto

发明人： Yuta Araki ,  Shoji Otaka ,  Toru Hashimoto

IPC分类号： H04B1/04 ,  H03L5/00

CPC分类号： H03L7/08 ,  H03D3/007 ,  H03F1/56 ,  H03F3/245 ,  H03F2200/211 ,  H03F2200/451 ,  H03F2200/453

摘要： A MOS resistance controlling device includes: a plurality of MOS transistors having a first MOS transistor to N-th (the integer N is larger than 1) MOS transistor being serially connected, the source of the first MOS transistor being set to a first reference potential, the drain the N-th MOS transistor being set to a second reference potential, and the drain of an I-th MOS transistor being connected to the source of an I+1-th MOS transistor, where I is an integer from 1 to N−1; a current source which is electrically disposed at connection node between the drain of the N-th MOS transistors and the second reference potential; and an operational amplifier having a first input terminal being supplied with a third reference potential, a second input terminal connected with the connection node and an output terminal being connected with gates of the MOS transistors.

摘要翻译： MOS电阻控制装置包括：多个MOS晶体管，其具有串联连接的第一MOS晶体管至第N（整数N大于1）的MOS晶体管，第一MOS晶体管的源极被设置为第一参考电位 ，第N个MOS晶体管的漏极被设置为第二参考电位，并且第一MOS晶体管的漏极连接到第I + 1个MOS晶体管的源极，其中I是从1到 N-1; 电流源，电流配置在第N个MOS晶体管的漏极与第2基准电位之间的连接节点处; 以及具有被提供有第三参考电位的第一输入端的运算放大器，与所述连接节点连接的第二输入端和与所述MOS晶体管的栅极连接的输出端。

公开(公告)号：US08060038B2

公开(公告)日：2011-11-15

申请号：US12188022

申请日：2008-08-07

申请人： Shoji Otaka ,  Yuta Araki ,  Toru Hashimoto

发明人： Shoji Otaka ,  Yuta Araki ,  Toru Hashimoto

IPC分类号： H04B1/04 ,  H04B1/02

CPC分类号： H04B1/0475 ,  H03F1/34 ,  H03F3/24 ,  H04B2001/0433

摘要： A radio transmitter including a combiner which combines input I/Q signals with feedback I/Q signals, a power amplifier which amplifies the quadrature modulated signal, a detector which detects amplitude and phase differences between the input and feedback I/Q signals, a switch to turn on and off the feedback I/Q signals, a generator to generate control signals which minimizes the amplitude difference and the phase difference, in a state where a transmission power is set, during for a period during which the switch is turned off, an amplitude adjuster which adjusts an amplitude of the feedback RF signal, during a period during which the switch is turned on, and a phase adjuster which adjusts a phase of the local signal, during the period during which the switch is turned on.

摘要翻译： 一种无线电发射机，包括将输入I / Q信号与反馈I / Q信号组合的组合器，放大正交调制信号的功率放大器，检测输入和反馈I / Q信号之间的幅度和相位差的检测器，开关 打开和关闭反馈I / Q信号的发生器，用于产生控制信号，在发送功率被设定的状态下，在关闭开关的时段期间使幅度差和相位差最小化的控制信号， 幅度调节器，其在开关导通的时段期间调整反馈RF信号的幅度;以及相位调节器，其在开关接通期间调节本地信号的相位。

公开(公告)号：US20080204107A1

公开(公告)日：2008-08-28

申请号：US11936214

申请日：2007-11-07

申请人： Yuta Araki ,  Shoji Otaka ,  Toru Hashimoto

发明人： Yuta Araki ,  Shoji Otaka ,  Toru Hashimoto

IPC分类号： H03L5/00

CPC分类号： H01L27/0802 ,  H03H11/245

摘要： A MOS resistance controlling device includes: a plurality of MOS transistors having a first MOS transistor to N-th (the integer N is larger than 1) MOS transistor being serially connected, the source of the first MOS transistor being set to a first reference potential, the drain the N-th MOS transistor being set to a second reference potential, and the drain of an I-th MOS transistor being connected to the source of an I+1-th MOS transistor, where I is an integer from 1 to N−1; a current source which is electrically disposed at connection node between the drain of the N-th MOS transistors and the second reference potential; and an operational amplifier having a first input terminal being supplied with a third reference potential, a second input terminal connected with the connection node and an output terminal being connected with gates of the MOS transistors.

摘要翻译： MOS电阻控制装置包括：多个MOS晶体管，其具有串联连接的第一MOS晶体管至第N（整数N大于1）的MOS晶体管，第一MOS晶体管的源极被设置为第一参考电位 ，第N个MOS晶体管的漏极被设置为第二参考电位，并且第一MOS晶体管的漏极连接到第I + 1个MOS晶体管的源极，其中I是从1到 N-1; 电流源，电流配置在第N个MOS晶体管的漏极与第2基准电位之间的连接节点处; 以及具有被提供有第三参考电位的第一输入端的运算放大器，与所述连接节点连接的第二输入端和与所述MOS晶体管的栅极连接的输出端。

公开(公告)号：US07501892B2

公开(公告)日：2009-03-10

申请号：US11755869

申请日：2007-05-31

申请人： Shoji Otaka ,  Yuta Araki

发明人： Shoji Otaka ,  Yuta Araki

IPC分类号： H03F3/45

CPC分类号： H03F3/45183 ,  H03F1/3211 ,  H03F3/24 ,  H03F2200/357 ,  H03F2200/456 ,  H03F2203/45288 ,  H03F2203/45362 ,  H03F2203/45466 ,  H03G1/0023

摘要： An amplifier circuit according to the present invention comprises: a first differential amplifier circuit including a first transistor having a gate terminal forming a first input node, a second transistor having a gate terminal forming a second input node and having a dimensional ratio with respect to the first transistor of K:M (where K>M), and a first current source that supplies a first current to a source terminal of the first transistor and a source terminal of the second transistor; a second differential amplifier circuit including a third transistor having a gate terminal forming a third input node, a fourth transistor having a gate terminal forming a fourth input node and having a dimensional ratio with respect to the third transistor of M:K, and a second current source that supplies a second current to a source terminal of the third transistor and a source terminal of the fourth transistor, the second differential amplifier circuit having a same gain as the first differential amplifier circuit; and a third differential amplifier circuit including a fifth transistor having a gate terminal forming a fifth input node, a sixth transistor having a gate terminal forming a sixth input node and having a dimensional ratio with respect to the fifth transistor of 1:1, and a variable current source that supplies a third current to a source terminal of the fifth transistor and a source terminal of the sixth transistor, wherein the third differential amplifier circuit combines the third current and the fifth transistor so that a gain of the third differential amplifier circuit is greater than a gain of the first differential amplifier circuit when the third current is a first magnitude, and the gain of the third differential amplifier circuit is lower than the gain of the first differential amplifier circuit when the third current is a second magnitude that differs from the first magnitude.

摘要翻译： 根据本发明的放大器电路包括：第一差分放大器电路，包括具有形成第一输入节点的栅极端子的第一晶体管，第二晶体管，具有形成第二输入节点的栅极端子，并且具有相对于 第一晶体管K：M（其中K> M）和第一电流源，其向第一晶体管的源极端子和第二晶体管的源极端子提供第一电流; 第二差分放大器电路，包括具有形成第三输入节点的栅极端子的第三晶体管，第四晶体管，具有形成第四输入节点的栅极端子，并且具有相对于M：K的第三晶体管的尺寸比，第二晶体管的第二 向第三晶体管的源极端子和第四晶体管的源极端子提供第二电流的电流源，第二差分放大器电路具有与第一差分放大器电路相同的增益; 以及第三差分放大电路，包括具有形成第五输入节点的栅极端子的第五晶体管，第六晶体管，具有形成第六输入节点的栅极端子，并且具有相对于第五晶体管的尺寸比为1:1，以及 向第五晶体管的源极端子和第六晶体管的源极端子提供第三电流的可变电流源，其中第三差分放大器电路组合第三电流和第五晶体管，使得第三差分放大器电路的增益为 大于第三差分放大器电路的增益，当第三电流是第一幅度时，第三差分放大器电路的增益低于第一差分放大器电路的增益， 第一大。

公开(公告)号：US20080068082A1

公开(公告)日：2008-03-20

申请号：US11755869

申请日：2007-05-31

申请人： Shoji Otaka ,  Yuta Araki

发明人： Shoji Otaka ,  Yuta Araki

IPC分类号： H03F3/45

CPC分类号： H03F3/45183 ,  H03F1/3211 ,  H03F3/24 ,  H03F2200/357 ,  H03F2200/456 ,  H03F2203/45288 ,  H03F2203/45362 ,  H03F2203/45466 ,  H03G1/0023

摘要： An amplifier circuit according to the present invention comprises: a first differential amplifier circuit including a first transistor having a gate terminal forming a first input node, a second transistor having a gate terminal forming a second input node and having a dimensional ratio with respect to the first transistor of K:M (where K>M), and a first current source that supplies a first current to a source terminal of the first transistor and a source terminal of the second transistor; a second differential amplifier circuit including a third transistor having a gate terminal forming a third input node, a fourth transistor having a gate terminal forming a fourth input node and having a dimensional ratio with respect to the third transistor of M:K, and a second current source that supplies a second current to a source terminal of the third transistor and a source terminal of the fourth transistor, the second differential amplifier circuit having a same gain as the first differential amplifier circuit; and a third differential amplifier circuit including a fifth transistor having a gate terminal forming a fifth input node, a sixth transistor having a gate terminal forming a sixth input node and having a dimensional ratio with respect to the fifth transistor of 1:1, and a variable current source that supplies a third current to a source terminal of the fifth transistor and a source terminal of the sixth transistor, wherein the third differential amplifier circuit combines the third current and the fifth transistor so that a gain of the third differential amplifier circuit is greater than a gain of the first differential amplifier circuit when the third current is a first magnitude, and the gain of the third differential amplifier circuit is lower than the gain of the first differential amplifier circuit when the third current is a second magnitude that differs from the first magnitude.

摘要翻译： 根据本发明的放大器电路包括：第一差分放大器电路，包括具有形成第一输入节点的栅极端子的第一晶体管，第二晶体管，具有形成第二输入节点的栅极端子，并且具有相对于 第一晶体管K：M（其中K> M）和第一电流源，其向第一晶体管的源极端子和第二晶体管的源极端子提供第一电流; 第二差分放大器电路，包括具有形成第三输入节点的栅极端子的第三晶体管，第四晶体管，具有形成第四输入节点的栅极端子，并且具有相对于M：K的第三晶体管的尺寸比，第二晶体管的第二 向第三晶体管的源极端子和第四晶体管的源极端子提供第二电流的电流源，第二差分放大器电路具有与第一差分放大器电路相同的增益; 以及第三差分放大电路，包括具有形成第五输入节点的栅极端子的第五晶体管，第六晶体管，具有形成第六输入节点的栅极端子，并且具有相对于第五晶体管的尺寸比为1:1，以及 向第五晶体管的源极端子和第六晶体管的源极端子提供第三电流的可变电流源，其中第三差分放大器电路组合第三电流和第五晶体管，使得第三差分放大器电路的增益为 大于第三差分放大器电路的增益，当第三电流是第一幅度时，第三差分放大器电路的增益低于第一差分放大器电路的增益， 第一大。

公开(公告)号：US09787716B2

公开(公告)日：2017-10-10

申请号：US12269523

申请日：2008-11-12

申请人： Keisuke Mera ,  Yusuke Doi ,  Takafumi Sakamoto ,  Toshiyuki Umeda ,  Shoji Otaka

发明人： Keisuke Mera ,  Yusuke Doi ,  Takafumi Sakamoto ,  Toshiyuki Umeda ,  Shoji Otaka

IPC分类号： H04L29/06 ,  H04W52/02 ,  G06F7/04 ,  G06F12/00 ,  G06F12/14 ,  G06F13/00 ,  G06F17/30 ,  H04W12/06

CPC分类号： H04L63/166 ,  H04L63/08 ,  H04W12/06 ,  H04W52/0229 ,  Y02D70/00 ,  Y02D70/20

摘要： A power-saving control apparatus includes a memory storing first to Nth different authentication codes, determines, every time a signal including an authentication code is received, whether the authentication code in the received signal is a valid code which matches one of the authentication codes in the memory, outputs an operation signal to a main apparatus when the authentication code in the received signal is determined to be the valid code, and generates a new authentication code, when (a) the number of times the authentication code in each received signal matches a first authentication code of the authentication codes in the memory is equal to a predetermined value or (b) the authentication code in the received signal matches a second or subsequent authentication code of the authentication codes in the memory, to delete one of the authentication codes in the memory, and to store the new authentication code in the memory.

公开(公告)号：US09219459B2

公开(公告)日：2015-12-22

申请号：US13614110

申请日：2012-09-13

申请人： Toshiyuki Umeda ,  Shoji Otaka

发明人： Toshiyuki Umeda ,  Shoji Otaka

IPC分类号： G08C19/16 ,  H03G3/30 ,  H04B1/30

CPC分类号： H03G3/3089 ,  H04B1/30

摘要： A receiving device includes a rectifier configured to rectify a received signal and a bias supply unit configured to intermittently supply the rectifier with a bias voltage corresponding to a threshold voltage of the rectifier. The receiving device further includes a detector configured to detect the received signal based on an output of the rectifier and a controller configured to control the bias supply unit to stop supplying the bias voltage upon detection of the received signal by the detector.

摘要翻译： 接收装置包括整流器，用于对接收到的信号进行整流;以及偏置电源单元，该偏置电源单元配置成以与整流器的阈值电压相对应的偏置电压间歇地向整流器供电。 接收装置还包括检测器，其被配置为基于整流器的输出检测接收到的信号;以及控制器，被配置为控制偏置电源单元在检测器检测到接收到的信号时停止提供偏置电压。

公开(公告)号：US08655295B2

公开(公告)日：2014-02-18

申请号：US13370535

申请日：2012-02-10

申请人： Tsuyoshi Kogawa ,  Koji Ogura ,  Shoji Otaka ,  Hiroaki Ishihara

发明人： Tsuyoshi Kogawa ,  Koji Ogura ,  Shoji Otaka ,  Hiroaki Ishihara

IPC分类号： H04B1/06

CPC分类号： H04B17/318

摘要： According to one embodiment, a receiving apparatus includes a variable gain amplifier, comparator, and signal processor. The comparator compares a signal level of the second signal with a first threshold to generate a third signal, a signal level of the third signal being set to a high signal if the signal level of the second signal is greater than the first threshold. The signal processor determines presence of a signal if a rate of high signals in third signals for a period is greater than a second threshold. The second threshold is set to a first value when the control of the gain is performed and set to a second value when the demodulation processing is performed. The first value is greater than the second value.

摘要翻译： 根据一个实施例，接收设备包括可变增益放大器，比较器和信号处理器。 比较器将第二信号的信号电平与第一阈值进行比较以产生第三信号，如果第二信号的信号电平大于第一阈值，则将第三信号的信号电平设置为高信号。 如果在一段时间内的第三信号中的高信号的速率大于第二阈值，则信号处理器确定信号的存在。 当执行增益的控制时，第二阈值被设置为第一值，并且当执行解调处理时将其设置为第二值。 第一个值大于第二个值。