Schmitt trigger with gated transition level control
    5.
    发明授权
    Schmitt trigger with gated transition level control 有权
    施密特触发器具有门控过渡电平控制

    公开(公告)号:US08203370B2

    公开(公告)日:2012-06-19

    申请号:US12494621

    申请日:2009-06-30

    IPC分类号: H03K3/00

    CPC分类号: H03K3/3565 H03K5/088

    摘要: A Schmitt trigger comprises first and second circuitry. The first circuitry receives an input voltage and provides an output voltage at either a logical “low” or a logical “high” voltage level responsive to the input voltage and a first bias voltage. The second circuitry connects to the first circuitry to generate a second bias current for generating the output voltage. The second bias current is larger than the first bias current. The Schmitt trigger operates in a low power mode of operation using only the first bias voltage to maintain the logical “low” voltage level or the logical “high” voltage level at a substantially constant level. In a high power mode of operation the Schmitt trigger uses the second bias voltage during transition periods between the logical “low” voltage level and the logical “high” voltage level.

    摘要翻译: 施密特触发器包括第一和第二电路。 第一电路接收输入电压并且响应于输入电压和第一偏置电压在逻辑“低”或逻辑“高”电压电平提供输出电压。 第二电路连接到第一电路以产生用于产生输出电压的第二偏置电流。 第二偏置电流大于第一偏置电流。 施密特触发器仅在第一偏置电压下工作在低功耗工作模式,以将逻辑“低”电压电平或逻辑“高”电压电平维持在基本恒定的水平。 在高功率工作模式下,施密特触发器在逻辑“低”电压电平和逻辑“高”电压电平之间的过渡期间使用第二偏置电压。

    LOW-POWER VOLTAGE REGULATOR
    6.
    发明申请
    LOW-POWER VOLTAGE REGULATOR 审中-公开
    低功率电压调节器

    公开(公告)号:US20110050198A1

    公开(公告)日:2011-03-03

    申请号:US12551788

    申请日:2009-09-01

    IPC分类号: G05F3/16

    CPC分类号: G05F3/242 G05F1/607

    摘要: A technique for reducing power dissipation and circuit area for a high voltage application includes creating a low-voltage, local power supply for use with local circuitry. In at least one embodiment of the invention, an apparatus includes an output node configured to provide a regulated output voltage. The apparatus includes a variable current source coupled to a first power supply node, wherein the variable current source is configured to provide an output current to the output node based on a control signal on a control node. The apparatus includes a feedback circuit configured to generate the control signal based on a mirrored current. The mirrored current is a mirrored version of a residual current flowing between the output node and a second power supply node. The regulated output voltage has a voltage level less than the voltage level on the first power supply node.

    摘要翻译: 用于降低功率耗散和高电压应用的电路面积的技术包括产生用于本地电路的低电压本地电源。 在本发明的至少一个实施例中,一种装置包括被配置成提供调节输出电压的输出节点。 该装置包括耦合到第一电源节点的可变电流源,其中可变电流源被配置为基于控制节点上的控制信号向输出节点提供输出电流。 该装置包括被配置为基于镜像电流产生控制信号的反馈电路。 镜像电流是在输出节点和第二电源节点之间流动的剩余电流的镜像版本。 调节输出电压具有小于第一电源节点上的电压电平的电压电平。

    DIGITAL TO ANALOG CONVERTER
    7.
    发明申请
    DIGITAL TO ANALOG CONVERTER 有权
    数字到模拟转换器

    公开(公告)号:US20130222162A1

    公开(公告)日:2013-08-29

    申请号:US13408173

    申请日:2012-02-29

    IPC分类号: H03M1/10 H03M1/66

    摘要: An input digital signal is converted to an analog signal using a main digital to analog converter (DAC) and a sub DAC. An offset value is subtracted from the input digital signal to generate an offset adjusted digital signal. The main DAC converts the offset adjusted digital signal to a first analog signal. A second digital signal is generated based on the offset value and a correction factor determined, at least in part, during calibration of the main DAC. The sub DAC converts the second digital to a second analog signal, which when combined with the first analog signal, provides an analog representation of the input digital signal.

    摘要翻译: 使用主数模转换器(DAC)和子DAC将输入数字信号转换为模拟信号。 从输入数字信号中减去偏移值,以生成偏移调整数字信号。 主DAC将偏移调整后的数字信号转换为第一个模拟信号。 基于偏移值和至少部分地在主DAC的校准期间确定的校正因子来生成第二数字信号。 子DAC将第二数字转换为第二模拟信号,当与第一模拟信号组合时,其提供输入数字信号的模拟表示。

    Digital to analog converter
    8.
    发明授权
    Digital to analog converter 有权
    数模转换器

    公开(公告)号:US08681026B2

    公开(公告)日:2014-03-25

    申请号:US13408173

    申请日:2012-02-29

    IPC分类号: H03M1/06

    摘要: An input digital signal is converted to an analog signal using a main digital to analog converter (DAC) and a sub DAC. An offset value is subtracted from the input digital signal to generate an offset adjusted digital signal. The main DAC converts the offset adjusted digital signal to a first analog signal. A second digital signal is generated based on the offset value and a correction factor determined, at least in part, during calibration of the main DAC. The sub DAC converts the second digital to a second analog signal, which when combined with the first analog signal, provides an analog representation of the input digital signal.

    摘要翻译: 使用主数模转换器(DAC)和子DAC将输入数字信号转换为模拟信号。 从输入数字信号中减去偏移值,以生成偏移调整数字信号。 主DAC将偏移调整后的数字信号转换为第一个模拟信号。 基于偏移值和至少部分地在主DAC的校准期间确定的校正因子来生成第二数字信号。 子DAC将第二数字转换为第二模拟信号,当与第一模拟信号组合时,该模拟信号提供输入数字信号的模拟表示。

    Successive approximation register analog-to-digital converter with multiple capacitive sampling circuits and method
    9.
    发明授权
    Successive approximation register analog-to-digital converter with multiple capacitive sampling circuits and method 有权
    具有多个电容采样电路和方法的逐次逼近寄存器模数转换器

    公开(公告)号:US08952839B2

    公开(公告)日:2015-02-10

    申请号:US13732113

    申请日:2012-12-31

    摘要: A circuit includes a comparator including a first input, a second input, and an output. The circuit further includes a plurality of capacitive sampling circuits configured to be selectively coupled to the first and second inputs. Each of the plurality of capacitive sampling circuits includes first and second capacitors, and includes first and second conversion switches configured to selectively couple the first and second capacitors to the first and second inputs, respectively. The first and second conversion switches of a selected one of the plurality of capacitive sampling circuits are closed to couple the selected one to the first and second inputs of the comparator during a conversion phase.

    摘要翻译: 电路包括比较器,其包括第一输入端,第二输入端和输出端。 电路还包括被配置为选择性地耦合到第一和第二输入的多个电容性采样电路。 多个电容性采样电路中的每一个包括第一和第二电容器,并且包括被配置为分别将第一和第二电容器选择性地耦合到第一和第二输入端的第一和第二转换开关。 多个电容性采样电路中的所选择的一个电容性采样电路的第一和第二转换开关闭合,以在转换阶段将所选择的一个耦合到比较器的第一和第二输入端。

    Successive Approximation Register Analog-to-Digital Converter with Multiple Capacitive Sampling Circuits and Method
    10.
    发明申请
    Successive Approximation Register Analog-to-Digital Converter with Multiple Capacitive Sampling Circuits and Method 有权
    具有多个电容采样电路的连续近似寄存器模数转换器和方法

    公开(公告)号:US20140184435A1

    公开(公告)日:2014-07-03

    申请号:US13732113

    申请日:2012-12-31

    IPC分类号: H03M1/38 H03K5/24

    摘要: A circuit includes a comparator including a first input, a second input, and an output. The circuit further includes a plurality of capacitive sampling circuits configured to be selectively coupled to the first and second inputs. Each of the plurality of capacitive sampling circuits includes first and second capacitors, and includes first and second conversion switches configured to selectively couple the first and second capacitors to the first and second inputs, respectively. The first and second conversion switches of a selected one of the plurality of capacitive sampling circuits are closed to couple the selected one to the first and second inputs of the comparator during a conversion phase.

    摘要翻译: 电路包括比较器,其包括第一输入端,第二输入端和输出端。 电路还包括被配置为选择性地耦合到第一和第二输入的多个电容性采样电路。 多个电容性采样电路中的每一个包括第一和第二电容器,并且包括被配置为分别将第一和第二电容器选择性地耦合到第一和第二输入端的第一和第二转换开关。 多个电容性采样电路中的所选择的一个电容性采样电路的第一和第二转换开关闭合,以在转换阶段将所选择的一个耦合到比较器的第一和第二输入端。