公开(公告)号：US20240345640A1

公开(公告)日：2024-10-17

申请号：US18481990

申请日：2023-10-05

Applicant: ASPEED Technology Inc.

Inventor： Shih-Fang Chen ,  Chin-Ting Kuo ,  Chia-Wei Wang ,  Chih-Chiang Mao

IPC: G06F1/24

CPC classification number: G06F1/24

Abstract: Embodiments of the disclosure provide a method for resetting a processor and a computer device. The method includes: obtaining an image file corresponding to a coprocessor by a first component of the computer device, and loading the image file into a reference space in a RAM by the first component; loading the image file stored in the reference space into a specific space corresponding to the coprocessor by a second component of the computer device and validating the image file stored in the specific space by the second component in response to determining that the coprocessor needs to be reset; and resetting the coprocessor by the second component based on the image file stored in the specific space in response to the second component determining that the image file stored in the specific space is valid.

公开(公告)号：US12051171B2

公开(公告)日：2024-07-30

申请号：US17833497

申请日：2022-06-06

Applicant: ASPEED Technology Inc.

Inventor： Chung-Yen Lu

IPC: G06T3/20 ,  G06T3/047 ,  G06T3/18 ,  G06T7/40 ,  G06T7/70 ,  G06V10/10 ,  G06V10/25 ,  G06V10/70 ,  G06V40/16 ,  H04N23/698

CPC classification number: G06T3/20 ,  G06T3/047 ,  G06T3/18 ,  G06T7/40 ,  G06T7/70 ,  G06V10/16 ,  G06V10/25 ,  G06V10/70 ,  G06V40/161 ,  H04N23/698 ,  G06T2207/20021 ,  G06T2207/20068 ,  G06T2207/30201

Abstract: An image processing system is disclosed, comprising a multiple-lens camera, a vertex list generator and an image processing apparatus. The multiple-lens camera captures a X-degree horizontal field of view (FOV) and a Y-degree vertical FOV to generate multiple lens images, where X

公开(公告)号：US20240126928A1

公开(公告)日：2024-04-18

申请号：US18073577

申请日：2022-12-02

Applicant: ASPEED Technology Inc.

Inventor： Chin-Ting Kuo ,  Chih-Chiang Mao

IPC: G06F21/64 ,  G06F9/4401 ,  H04L9/00 ,  H04L9/08 ,  H04L9/32

CPC classification number: G06F21/64 ,  G06F9/4401 ,  H04L9/0825 ,  H04L9/3247 ,  H04L9/50

Abstract: A data security verification method and an electronic apparatus are provided. In the data security verification method, when the electronic apparatus is powered on, a verification circuit verifies integrity of an executable image in a storage device. If verification fails, the verification circuit stops a host processor from executing the executable image. If the verification is successful, the verification circuit releases a host reset, and a processor reads and executes the executable image. When the processor reads the executable image, the verification circuit re-verifies the executable image, and the processor executes the executable image according to a verification result.

公开(公告)号：US20230377676A1

公开(公告)日：2023-11-23

申请号：US17883607

申请日：2022-08-09

Applicant: ASPEED Technology Inc.

Inventor： Hung-Ming Lin ,  Hung-Ju Huang

IPC: G11C29/52 ,  G11C29/02 ,  G11C7/10 ,  G06F7/58

CPC classification number: G11C29/52 ,  G11C29/022 ,  G11C7/1039 ,  G06F7/58

Abstract: The disclosure provides an integrated circuit and an operation method and an inspection method thereof. The integrated circuit includes a one-time programmable (OTP) memory, an identifier generation circuit, and a memory controller. The identifier generation circuit generates a random number, and performs an error-detection-code encoding operation on the random number to generate an identifier with an error-detection code. The memory controller writes the identifier generated by the identifier generation circuit into the OTP memory. The identifier generation circuit reads the identifier from the OTP memory through the memory controller, and performs an error-detection-code decoding operation on the identifier provided by the memory controller to determine whether an error of the identifier from the OTP memory is correctable. When it is determined that the error of the identifier from the OTP memory is not correctable, the writing of the identifier is deemed failed.

公开(公告)号：US20230022221A1

公开(公告)日：2023-01-26

申请号：US17412272

申请日：2021-08-26

Applicant: ASPEED Technology Inc.

Inventor： Jyun-Kai Syong ,  Chen-Wei Chou

IPC: G06T7/20 ,  G06K9/32

Abstract: An object tracking method and an object tracking apparatus, which are adapted for a low latency application, are provided. In the method, an object detection is performed on one of continuous image frames. The objection detection is configured to identify a target. The continuous image frames are temporarily stored. An objection tracking is performed on the temporarily stored continuous image frames according to a result of the object detection. The objection tracking is configured to associate the target in one of the continuous image frames with the target in another of the continuous image frames. Accordingly, the accuracy of object tracking may be improved, and the requirement for low latency may be satisfied.

公开(公告)号：US11502712B2

公开(公告)日：2022-11-15

申请号：US17229832

申请日：2021-04-13

Applicant: ASPEED Technology Inc.

Inventor： Hung-Ming Lin ,  Chih-Chiang Mao

IPC: H04B1/38

Abstract: A signal transceiving system and a signal receiver thereof are provided. The signal transceiving system includes a signal transmitter. The signal transmitter includes a first data buffer, a comparator, and an encoder. The first data buffer receives transmitted data and provides previously transmitted data. The comparator receives currently transmitted data and receives the previously transmitted data. The comparator compares, in a first mode, the previously transmitted data with the currently transmitted data to generate a data variation information. The encoder generates, in the first mode, at least one index value and a corresponding instruction signal according to the data variation information. The signal transmitter sends the at least one index value which is a serial signal and the instruction signal to a signal receiver.

公开(公告)号：US11496710B2

公开(公告)日：2022-11-08

申请号：US17233047

申请日：2021-04-16

Applicant: ASPEED Technology Inc.

Inventor： Chen-Wei Chou ,  Chien-Chou Yang

IPC: H04N7/15 ,  H04N7/14 ,  G09G5/39

Abstract: An image display method applicable to a video conferencing system with a wide-angle webcam is disclosed. The wide-angle webcam is used to capture a panoramic image having an aspect ratio greater than or equal to 2:1. The method includes: framing multiple regions of interest (ROIs) according to the panoramic image, each ROI having at least one of attributes; selecting one from predetermined frame layouts as an output frame layout according to whether to insert a portion of the panoramic image and attributes, positions and the number of the ROIs; and inserting at least one of the portion of the panoramic image and the ROIs into corresponding windows in the output frame layout to form a composite frame according to the attributes of the ROIs.

公开(公告)号：US10104288B2

公开(公告)日：2018-10-16

申请号：US15427504

申请日：2017-02-08

Applicant: ASPEED Technology Inc.

Inventor： Pei-Hen Hung ,  Chung-Yen Lu ,  Kuo-Wei Yeh ,  Jing-Chuan Chen

IPC: H04N5/232 ,  G06T3/40 ,  G06T3/00 ,  G06T11/60

Abstract: A vertex processing device applied in an image processing system having an image capture module is disclosed. The image capture module generates camera images. The vertex processing device comprises a coefficient interpolation unit and a coordinate modifying unit. The coefficient interpolation unit generates an interpolated warping coefficient for each camera image with respect to each vertex from a vertex list based on n number of warping coefficients and its original texture coordinates in each camera image. The coordinate modifying unit calculates modified texture coordinates in each camera image for each vertex according to the interpolated warping coefficient and its original texture coordinates in each camera image. The vertex list comprises vertices with data structures that define vertex mapping between the camera images and a panoramic image. The n number of warping coefficients correspond to n number of overlap regions in the panoramic image.

公开(公告)号：US09466089B2

公开(公告)日：2016-10-11

申请号：US14508851

申请日：2014-10-07

Applicant: ASPEED TECHNOLOGY INC.

Inventor： Chung-Yen Lu

IPC: G09G5/00 ,  G06T1/20 ,  H04N19/85

CPC classification number: G06T1/20 ,  G06F3/14 ,  G09G5/00 ,  G09G2350/00 ,  G09G2370/022 ,  H04N19/85

Abstract: A signal processor of the invention includes a host processor, a command queue, a graphics decoding circuit, a video decoding circuit, a composition engine and two display buffers. The host processor generates graphics commands and sets a video flag to active based on graphics encoded data, video encoded data and mask encoded data from a network. The command queue asserts a control signal according to the graphics commands. The graphics decoding circuit generates the graphics frame and two surface mask while the video decoding circuit generates the video frame and a video mask. The composition engine transfers the graphics frame, the video frame or a content of one of two display buffers to the other display buffer according to the video mask and the two surface masks when the control signal is asserted or when the video flag is active.

Abstract translation: 本发明的信号处理器包括主处理器，命令队列，图形解码电路，视频解码电路，组合引擎和两个显示缓冲器。 主机处理器根据图形编码数据，视频编码数据和来自网络的掩码编码数据，生成图形命令并将视频标志设置为有效。 命令队列根据图形命令声明控制信号。 图形解码电路在视频解码电路产生视频帧和视频掩码的同时产生图形帧和两个表面掩码。 组合引擎在控制信号被断言时或当视频标志有效时，根据视频掩码和两个表面掩模将图形帧，视频帧或两个显示缓冲器之一的内容传送到另一显示缓冲器。

公开(公告)号：US08698531B1

公开(公告)日：2014-04-15

申请号：US13759939

申请日：2013-02-05

Applicant: Aspeed Technology Inc.

Inventor： Fu-Chou Hsu ,  Hung-Ju Huang ,  Chung-Yen Lu

IPC: H03K3/02

CPC classification number: G06F15/177

Abstract: An integrated circuit with automatic configuration is disclosed. The integrated circuit comprises a plurality of controllers and a clock detection device. The controllers share a plurality of common pins. The clock detection device coupled to a specified common pin for performing clock detection operations on an external clock signal through the specified common pin according to a plurality of predetermined thresholds and generating a plurality of control signals to the controllers so that only one controller is enabled and performs signal transmission through the common pins.

Abstract translation: 公开了具有自动配置的集成电路。 集成电路包括多个控制器和时钟检测装置。 控制器共享多个公共引脚。 时钟检测装置耦合到指定的公共引脚，用于根据多个预定阈值通过指定的公共引脚对外部时钟信号执行时钟检测操作，并向控制器生成多个控制信号，使得只有一个控制器被使能， 通过公共引脚进行信号传输。