公开(公告)号：US20220376172A1

公开(公告)日：2022-11-24

申请号：US17871147

申请日：2022-07-22

申请人： Avalanche Technology, Inc.

发明人： Zihui Wang ,  Yiming Huai

IPC分类号： H01L43/08 ,  G11C11/15 ,  G11C11/16 ,  H01L43/02 ,  H01F10/32 ,  H01F41/30 ,  H01L27/22 ,  H01L29/66 ,  H01L43/10

摘要： The present invention is directed to a magnetic memory element including a magnetic free layer structure incorporating two magnetic free layers separated by a perpendicular enhancement layer (PEL) and having a variable magnetization direction substantially perpendicular to layer planes thereof; an insulating tunnel junction layer formed adjacent to the magnetic free layer structure; a magnetic reference layer structure formed adjacent to the insulating tunnel junction layer opposite the magnetic free layer structure; an anti-ferromagnetic coupling layer formed adjacent to the magnetic reference layer structure; and a magnetic fixed layer formed adjacent to the anti-ferromagnetic coupling layer. The magnetic reference layer structure includes first, second, and third magnetic reference layers separated by two PELs and having a first invariable magnetization direction substantially perpendicular to layer planes thereof. The magnetic fixed layer has a second invariable magnetization direction substantially opposite to the first invariable magnetization direction.

公开(公告)号：US20210390995A1

公开(公告)日：2021-12-16

申请号：US16900470

申请日：2020-06-12

申请人： Avalanche Technology, Inc.

发明人： Dean K. Nobunaga

IPC分类号： G11C11/16

摘要： The present invention is directed to a nonvolatile memory device including a plurality of memory cells arranged in rows and columns, a plurality of word lines with each connected to a respective row of the memory cells along a row direction, a plurality of bit lines with each connected to a respective column of the memory cells along a column direction; a column decoder connected to the bit lines; a plurality of sense amplifiers connected to the column decoder; and a plurality of sense amplifier control circuits. Each of the sense amplifiers is connected to a unique one of the sense amplifier control circuits. Each of the sense amplifier control circuits includes a current detector circuit for detecting a sensing current, a current booster circuit for boosting the sensing current, and a timer circuit for providing a delayed trigger for a respective one of the sense amplifiers connected thereto.

公开(公告)号：US20210159399A1

公开(公告)日：2021-05-27

申请号：US17156562

申请日：2021-01-23

申请人： Avalanche Technology, Inc.

发明人： Yiming Huai ,  Zihui Wang

IPC分类号： H01L43/08 ,  G11C11/15 ,  G11C11/16 ,  H01L43/02 ,  H01L43/10 ,  H01F10/32 ,  H01F41/30 ,  H01L27/22 ,  H01L29/66

摘要： The present invention is directed to a magnetic memory element including a magnetic free layer structure incorporating three magnetic free layers separated by two perpendicular enhancement layers (PELs) and having a variable magnetization direction substantially perpendicular to layer planes thereof; an insulating tunnel junction layer formed adjacent to the magnetic free layer structure; a first magnetic reference layer formed adjacent to the insulating tunnel junction layer opposite the magnetic free layer structure; a second magnetic reference layer separated from the first magnetic reference layer by a third perpendicular enhancement layer; an anti-ferromagnetic coupling layer formed adjacent to the second magnetic reference layer; and a magnetic fixed layer formed adjacent to the anti-ferromagnetic coupling layer. The first and second magnetic reference layers have a first invariable magnetization direction substantially perpendicular to layer planes thereof. The magnetic fixed layer has a second invariable magnetization direction substantially opposite to the first invariable magnetization direction.

公开(公告)号：US10936327B2

公开(公告)日：2021-03-02

申请号：US16808099

申请日：2020-03-03

申请人： Avalanche Technology, Inc.

发明人： Ngon Van Le ,  Ravishankar Tadepalli

IPC分类号： G06F9/4401 ,  G06F15/78 ,  G11C14/00 ,  G11C11/16

摘要： The present invention is directed to a method for booting a system-on-chip (SoC) including the steps of directly executing a boot software from an on-chip magnetic random access memory (MRAM) residing on a same semiconductor as the SoC; directly executing an operating system software from an external MRAM by the SoC without loading the operating system into a volatile memory; and directly executing an application software from the external MRAM by the SoC, wherein the external MRAM is coupled to the SoC and is configured for storing the operating system software and the application software.

公开(公告)号：US10818731B1

公开(公告)日：2020-10-27

申请号：US16446532

申请日：2019-06-19

申请人： Avalanche Technology, Inc.

发明人： Kimihiro Satoh

IPC分类号： H01L27/24 ,  H01L43/02 ,  H01L45/00 ,  G11C11/16 ,  H01L27/22 ,  G11C13/00 ,  H01F10/32

摘要： The present invention is directed to a memory array including one or more memory layers, each of which includes a first plurality of memory cells and a second plurality of memory cells arranged in alternated odd and even columns, respectively; multiple odd horizontal lines with each connected to a respective odd column of the first plurality of memory cells; multiple even horizontal lines with each connected to a respective even column of the second plurality of memory cells; multiple transverse lines with each connected to one of the first plurality of memory cells and a respective one of the second plurality of memory cells disposed adjacent thereto along a row direction; and multiple vertical lines with each connected to a respective one of the multiple transverse lines. The odd horizontal lines collectively form fingers of a first comb structure and the even horizontal lines collectively form fingers of a second comb structure.

公开(公告)号：US10593727B2

公开(公告)日：2020-03-17

申请号：US15863825

申请日：2018-01-05

申请人： Avalanche Technology, Inc.

发明人： Hongxin Yang ,  Bing K. Yen ,  Jing Zhang

IPC分类号： H01L27/22 ,  H01L43/10 ,  H01L43/08 ,  H01L45/00 ,  G11C11/16 ,  G11C16/10

摘要： The present invention is directed to a memory cell that includes a magnetic tunnel junction (MTJ) memory element and a two-terminal selector element coupled in series. The MTJ memory element includes a magnetic free layer structure and a magnetic reference layer structure with an insulating tunnel junction layer interposed therebetween. The magnetic reference layer structure includes one or more magnetic reference layers having a first invariable magnetization direction substantially perpendicular to layer planes thereof. The two-terminal selector element includes a first inert electrode and a second inert electrode with a volatile switching layer interposed therebetween; a first active electrode formed adjacent to the first inert electrode; and a second active electrode formed adjacent to the second inert electrode. The volatile switching layer includes a plurality of metal-rich particles or clusters embedded in a matrix or at least one conductor layer interleaved with insulating layers.

公开(公告)号：US10361362B2

公开(公告)日：2019-07-23

申请号：US15815516

申请日：2017-11-16

申请人： Avalanche Technology, Inc.

发明人： Huadong Gan ,  Yiming Huai ,  Yuchen Zhou ,  Zihui Wang

IPC分类号： H01F10/32 ,  H01L43/08 ,  G11C11/16

摘要： The present invention is directed to a magnetic memory element including a magnetic free layer and a first magnetic reference layer with an insulating tunnel junction layer interposed therebetween; a second magnetic reference layer made of a material comprising cobalt and formed adjacent to the first magnetic reference layer opposite the insulating tunnel junction layer; an iridium layer formed adjacent to the second magnetic reference layer opposite the first magnetic reference layer; and a magnetic fixed layer formed adjacent to the iridium layer. The magnetic free layer has a variable magnetization direction substantially perpendicular to the layer plane thereof. The first and second magnetic reference layers have a first fixed magnetization direction substantially perpendicular to the layer planes thereof. The magnetic fixed layer has a second fixed magnetization direction that is substantially perpendicular to the layer plane thereof and is substantially opposite to the first fixed magnetization direction.

公开(公告)号：US10224367B2

公开(公告)日：2019-03-05

申请号：US15157607

申请日：2016-05-18

申请人： Avalanche Technology, Inc.

发明人： Hongxin Yang ,  Kimihiro Satoh ,  Xiaobin Wang

IPC分类号： H01L27/22 ,  H01L43/08 ,  H01L45/00 ,  H01L27/24

摘要： The present invention is directed to a memory device that includes an array of memory cells. Each of the memory cells includes a memory element connected to a two-terminal selector element. The two-terminal selector element includes a first electrode and a second electrode with a switching layer interposed therebetween. The switching layer includes a plurality of metal-rich clusters embedded in a nominally insulating matrix. One or more conductive paths are formed in the switching layer when an applied voltage to the memory cell exceeds a threshold level. Each of the memory cells may further include an intermediate electrode interposed between the memory element and the two-terminal selector element. The two-terminal selector element may further include a third electrode formed between the first electrode and the switching layer, and a fourth electrode formed between the second electrode and the switching layer.

公开(公告)号：US10177308B2

公开(公告)日：2019-01-08

申请号：US15618510

申请日：2017-06-09

申请人： Avalanche Technology, Inc.

发明人： Hongxin Yang ,  Dong Ha Jung ,  Jing Zhang ,  Bing K. Yen

IPC分类号： H01L43/12 ,  H01L43/08 ,  H01L27/22 ,  G11C11/16

摘要： The present invention is directed to a method for manufacturing a memory cell that includes a magnetic memory element electrically connected to a two-terminal selector. The method includes the steps of depositing a magnetic memory element film stack on a substrate; depositing a selector film stack on top of the magnetic memory element film stack; etching the selector film stack with an etch mask formed thereon to remove at least a switching layer in the selector film stack not covered by the etch mask, thereby forming a selector pillar; depositing a first conforming dielectric layer over the selector pillar and surrounding surface; etching a portion of the first conforming dielectric layer covering the surrounding surface to form a first protective sleeve around at least the switching layer of the selector pillar; and etching the magnetic memory element film stack using the etch mask and the first protective sleeve as a composite mask to form a memory cell pillar.

公开(公告)号：US10153017B2

公开(公告)日：2018-12-11

申请号：US15264847

申请日：2016-09-14

申请人： Avalanche Technology, Inc.

发明人： Hongxin Yang ,  Xiaobin Wang ,  Jing Zhang ,  Xiaojie Hao ,  Zihui Wang ,  Kimihiro Satoh

IPC分类号： G11C11/16 ,  H01L27/22 ,  H01L43/02

摘要： The present invention is directed to a method for sensing the resistance state of a memory cell that includes an MTJ memory element coupled to a two-terminal selector element in series. The method includes the steps of raising a cell voltage across the memory cell above a threshold voltage for the selector element to become conductive; decreasing the cell voltage to a first sensing voltage and measuring a first sensing current passing through the memory cell, the selector element being nominally conductive irrespective of the resistance state of the MTJ memory element at the first sensing voltage; and further decreasing the cell voltage to a second sensing voltage and measuring a second sensing current, the selector element being nominally conductive if the MTJ memory element is in the low resistance state or nominally insulative if the MTJ memory element is in the high resistance state at the second sensing voltage.