公开(公告)号：US20100141296A1

公开(公告)日：2010-06-10

申请号：US12595865

申请日：2008-12-10

Applicant: Neil Wood ,  David Rea ,  Bin Li

Inventor： Neil Wood ,  David Rea ,  Bin Li

IPC: H03K19/003 ,  H03K19/094

CPC classification number: H03K19/23

Abstract: A current mode logic voter circuit includes three two-input split NOR gates. Each two-input split NOR gate receives a corresponding pair of input signals and generates a pair of first output signals responsive to the input signals. A three input split NOR gate is coupled to the two-input split NOR gates to receive the first output signals and generates a second pair of output signals responsive to the first output signals from the two-input split NOR gates. The two and three-input split NOR gates can be formed from current mode logic buffer circuits, and in one embodiment in the three-input split NOR gate the buffer circuits are hardened.

Abstract translation: 电流模式逻辑选择电路包括三个双输入分频NOR门。 每个双输入分频NOR门接收相应的输入信号对，并根据输入信号产生一对第一输出信号。 三输入分频NOR门耦合到双输入分频NOR门以接收第一输出信号，并响应于来自双输入分频NOR门的第一输出信号产生第二对输出信号。 两个和三个输入的分频NOR门可以由电流模式逻辑缓冲电路形成，并且在一个实施例中，在三输入分频NOR门中，缓冲电路被硬化。