公开(公告)号：US4802113A

公开(公告)日：1989-01-31

申请号：US758665

申请日：1985-06-25

申请人： Katsumi Onishi ,  Yuji Oinaga ,  Kohei Otsuyama

发明人： Katsumi Onishi ,  Yuji Oinaga ,  Kohei Otsuyama

IPC分类号： G06F9/32 ,  G06F9/38 ,  G06F9/00

CPC分类号： G06F9/3804 ,  G06F9/321

摘要： According to the present invention, an instruction address register unit I for reading instructions and an instruction address register unit II for indicating the address of the instruction being executed in the pipeline are provided independently. The address of a branching instruction is held in the instruction address register unit II until said instruction passes through the pipeline, the content of instruction address register unit I is updated when branching of the branching instruction is determined, and thereby delay in reading an instruction after 8 bytes at the branching address can be reduced.

摘要翻译： PCT No.PCT / JP84 / 00535 Sec。 371日期1985年6月25日第 102（e）日期1985年6月25日PCT提交1984年11月8日PCT公布。 第WO85 / 02279号公报 1985年5月23日。根据本发明，独立地提供用于读取指令的指令地址寄存器单元I和用于指示正​​在流水线中执行的指令的地址的指令地址寄存器单元II。 分支指令的地址被保持在指令地址寄存器单元II中，直到所述指令通过流水线，当分支指令的分支被确定时，指令地址寄存器单元I的内容被更新，从而延迟读取指令 可以减少分支地址处的8个字节。

公开(公告)号：US4893274A

公开(公告)日：1990-01-09

申请号：US261298

申请日：1988-10-24

申请人： Isao Fukushi

发明人： Isao Fukushi

IPC分类号： H03K19/0944 ,  G11C8/06 ,  G11C11/417 ,  H03K3/356 ,  H03K5/00 ,  H03K19/0185

CPC分类号： G11C8/06 ,  H03K19/018521 ,  H03K3/356104

摘要： A semiconductor memory device including a plurality of level converters, each of the level converters including a bridge circuit constituted by four MOS transistors having one type of conductivity, gates of one pair of four transistors opposing each other receiving a first signal and gates of the other pair of four transistors opposing each other receiving a signal complementary to the first signal; a pair of complementary MOS inverter circuits to which a second signal and a signal complementary to the second signal are input, respectively, the outputs of the pair of inverter circuits being connected to a first pair of connecting points positioned alternately in the bridge circuit, respectively; and a flip-flop circuit connected between a second pair of connecting points positioned alternately in the bridge circuit, to thereby output a third signal and a signal complementary to the third signal from the second pair of connecting points, resepctively.

公开(公告)号：US4801899A

公开(公告)日：1989-01-31

申请号：US941370

申请日：1986-12-15

申请人： Hideo Ashida

发明人： Hideo Ashida

IPC分类号： H04L27/01 ,  H04L27/36 ,  H04L27/38 ,  H04L27/20 ,  H04L27/22

CPC分类号： H04L27/3854 ,  H04L27/367

摘要： A modulation device using multi-level digital signals includes: a pair of balanced mixers for carrying out quadrature amplitude modulation to deliver a quadrature amplitude modulated signal; input and output hybrid circuits, connected to carrier input terminals of the pair of balanced mixers, for supplying carrier inputs to the pair of balanced mixers; and a modulation characteristic compensation unit connected with input terminals of the pair of balanced mixers for supplying the pair of balanced mixers with orthogonal baseband input signals. A demodulation device with a use of multi-level digital signals including: a pair of balanced mixers for carrying out quadrature amplitude demodulation to deliver a pair of quadrature amplitude demodulated signals; first and second input hybrid circuits; and a demodulation characteristic compensation unit connected with output terminals of the pair of balanced mixers for deriving demodulation characteristic compensated orthogonal baseband signals from the pair of quadrature amplitude demodulated signals.

摘要翻译： 使用多电平数字信号的调制装置包括：一对平衡混频器，用于进行正交幅度调制以传送正交幅度调制信号; 输入和输出混合电路，连接到一对平衡混频器的载波输入端，用于向一对平衡混频器提供载波输入; 以及调制特性补偿单元，与所述一对平衡混频器的输入端连接，用于向一对平衡混频器提供正交的基带输入信号。 一种使用多电平数字信号的解调装置，包括：一对平衡混频器，用于进行正交幅度解调以提供一对正交幅度解调信号; 第一和第二输入混合电路; 以及解调特性补偿单元，与所述一对平衡混频器的输出端连接，用于从所述一对正交幅度解调信号中导出解调特性补偿的正交基带信号。