公开(公告)号：US20170074819A1

公开(公告)日：2017-03-16

申请号：US15122111

申请日：2014-03-28

申请人： Intel Corporation

发明人： Oguz H. ELIBOL

IPC分类号： G01N27/327 ,  G01N33/487 ,  C23C18/16 ,  C12Q1/68 ,  C23C14/34 ,  C23C16/455

CPC分类号： G01N27/3278 ,  C12Q1/6869 ,  C23C14/34 ,  C23C16/45525 ,  C23C18/1633 ,  G01N33/48721

摘要： An apparatus including a circuit substrate including a contact in a metal layer; and a transducer including a first electrode deposited on and coupled to a sidewall of the contact and a second electrode coupled to a conductor through which voltage can be applied, wherein the second electrode includes a profile aligned to the sidewall of the contact and separated from the first electrode by a gap. A method including forming a transducer adjacent a contact in a metal layer on a substrate, the transducer including a first electrode disposed on a sidewall of the contact and a second electrode coupled to a conductor through which voltage can be applied, wherein the second electrode includes a profile aligned to the sidewall of the contact and separated from the first electrode by a gap.

摘要翻译： 一种包括在金属层中包括接触的电路基板的设备; 以及换能器，其包括沉积在所述接触件的侧壁上并且耦合到所述接触件的侧壁的第一电极和耦合到可以施加电压的导体的第二电极，其中所述第二电极包括与所述接触件的侧壁对准的轮廓并与所述接触件分离 第一电极间隙。 一种方法，包括在衬底上的金属层中形成与接触件相邻的换能器，所述换能器包括设置在所述触点的侧壁上的第一电极和耦合到可以施加电压的导体的第二电极，其中所述第二电极包括 该轮廓与该接触件的侧壁对齐并且与该第一电极分开一间隙。

公开(公告)号：US20170125524A1

公开(公告)日：2017-05-04

申请号：US15405182

申请日：2017-01-12

申请人： Intel Corporation

发明人： RAVI PILLARISETTY ,  SANSAPTAK DASGUPTA ,  NITI GOEL ,  VAN H. LE ,  MARKO RADOSAVLJEVIC ,  GILBERT DEWEY ,  NILOY MUKHERJEE ,  MATTHEW V. METZ ,  WILLY RACHMADY ,  JACK T. KAVALIEROS ,  BENJAMIN CHU-KUNG ,  HAROLD W. KENNEL ,  STEPHEN M. CEA ,  ROBERT S. CHAU

IPC分类号： H01L29/10 ,  H01L29/165 ,  H01L29/20 ,  H01L21/762 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L29/16 ,  H01L29/267

CPC分类号： H01L29/785 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823462 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/165 ,  H01L29/20 ,  H01L29/267 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7851

摘要： Ge and III-V channel semiconductor devices having maximized compliance and free surface relaxation and methods of fabricating such Ge and III-V channel semiconductor devices are described. For example, a semiconductor device includes a semiconductor fin disposed above a semiconductor substrate. The semiconductor fin has a central protruding or recessed segment spaced apart from a pair of protruding outer segments along a length of the semiconductor fin. A cladding layer region is disposed on the central protruding or recessed segment of the semiconductor fin. A gate stack is disposed on the cladding layer region. Source/drain regions are disposed in the pair of protruding outer segments of the semiconductor fin.

公开(公告)号：US20170012126A1

公开(公告)日：2017-01-12

申请号：US15119674

申请日：2014-03-28

申请人： INTEL CORPORATION

发明人： Benjamin CHU-KUNG ,  Gilbert DEWEY ,  Van H. LE ,  Jack T. KAVALIEROS ,  Marko RADOSAVLJEVIC ,  Ravi PILLARISETTY ,  Han Wui THEN ,  Niloy MUKHERJEE ,  Sansaptak DASGUPTA

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L29/423 ,  H01L29/786

摘要： Vertical semiconductor devices having selectively regrown top contacts and method of fabricating vertical semiconductor devices having selectively regrown top contacts are described. For example, a semiconductor device includes a substrate having a surface. A first source/drain region is disposed on the surface of the substrate. A vertical channel region is disposed on the first source/drain region and has a first width parallel with the surface of the substrate. A second source/drain region is disposed on the vertical channel region and has a second width parallel with and substantially greater than the first width. A gate stack is disposed on and completely surrounds a portion of the vertical channel region.

摘要翻译： 描述了具有选择性再生长顶端触点的垂直半导体器件和制造具有选择性再生长顶端触点的垂直半导体器件的方法。 例如，半导体器件包括具有表面的衬底。 第一源极/漏极区域设置在衬底的表面上。 垂直沟道区域设置在第一源极/漏极区域上并且具有与衬底的表面平行的第一宽度。 第二源极/漏极区域设置在垂直沟道区域上并且具有与第一宽度平行并且基本上大于第一宽度的第二宽度。 栅堆叠设置在垂直沟道区的一部分上并完全环绕。

公开(公告)号：US20160172477A1

公开(公告)日：2016-06-16

申请号：US14909090

申请日：2013-09-27

申请人： INTEL CORPORATION

发明人： Gilbert DEWEY ,  Matthew V. METZ ,  Niloy MUKHERJEE ,  Robert S. CHAU ,  Marko RADOSAVLJEVIC ,  Ravi PILLARISETTY ,  Benjamin CHU-KUNG

IPC分类号： H01L29/778 ,  H01L29/78 ,  H01L29/66 ,  H01L29/205

CPC分类号： H01L29/7786 ,  H01L29/1054 ,  H01L29/205 ,  H01L29/66462 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

摘要： An apparatus including a heterostructure disposed on a substrate and defining a channel region, the heterostructure including a first material having a first band gap less than a band gap of a material of the substrate and a second material having a second band gap that is greater than the first band gap; and a gate stack on the channel region, wherein the second material is disposed between the first material and the gate stack. A method including forming a first material having a first band gap on a substrate; forming a second material having a second band gap greater than the first band gap on the first material; and forming a gate stack on the second material.

摘要翻译： 一种包括设置在衬底上并限定沟道区的异质结构的装置，所述异质结构包括具有小于所述衬底的材料的带隙的第一带隙的第一材料和具有大于所述衬底的材料的第二带隙的第二材料 第一个带隙; 以及栅极堆叠，其中所述第二材料设置在所述第一材料和所述栅极叠层之间。 一种方法，包括在基板上形成具有第一带隙的第一材料; 形成具有大于所述第一材料上的所述第一带隙的第二带隙的第二材料; 以及在所述第二材料上形成栅叠层。

公开(公告)号：US20190114283A1

公开(公告)日：2019-04-18

申请号：US16211924

申请日：2018-12-06

申请人： Intel Corporation

发明人： Manasi DEVAL ,  Nrupal JANI ,  Anjali SINGHAI ,  Parthasarathy SARANGAM ,  Mitu AGGARWAL ,  Neerav PARIKH ,  Kiran PATIL ,  Rajesh M. SANKARAN ,  Sanjay K. KUMAR ,  Utkarsh Y. KAKAIYA ,  Philip LANTZ ,  Kun TIAN

IPC分类号： G06F13/42 ,  G06F9/455

摘要： Examples may include a computing platform having a host driver to get a packet descriptor of a received packet stored in a receive queue and to modify the packet descriptor from a first format to a second format. The computing platform also includes a guest virtual machine including a guest driver coupled to the host driver, the guest driver to receive the modified packet descriptor and to read a packet buffer stored in the receive queue using the modified packet descriptor, the packet buffer corresponding to the packet descriptor.

公开(公告)号：US20170345476A1

公开(公告)日：2017-11-30

申请号：US15503359

申请日：2014-09-26

申请人： Intel Corporation

发明人： Mark L. DOCZY ,  Kaan OGUZ ,  Brian S. DOYLE ,  Charles C. KUO ,  Robert S. CHAU ,  Satyarth SURI

IPC分类号： G11C11/16 ,  H01L43/10 ,  H01L27/22 ,  H01L43/12 ,  H01F10/32

CPC分类号： G11C11/161 ,  H01F10/3286 ,  H01L27/222 ,  H01L43/10 ,  H01L43/12

摘要： A material layer stack for a magnetic tunneling junction, the material layer stack including a fixed magnetic layer; a dielectric layer; a free magnetic layer; and an amorphous electrically-conductive seed layer, wherein the fixed magnetic layer is disposed between the dielectric layer and the seed layer. A non-volatile memory device including a material stack including an amorphous electrically-conductive seed layer; and a fixed magnetic layer juxtaposed and in contact with the seed layer. A method including forming an amorphous seed layer on a first electrode of a memory device; forming a material layer stack on the amorphous seed layer, the material stack including a dielectric layer disposed between a fixed magnetic layer and a free magnetic layer, wherein the fixed magnetic layer.

公开(公告)号：US20160204246A1

公开(公告)日：2016-07-14

申请号：US14914102

申请日：2013-09-27

申请人： INTEL CORPORATION

发明人： RAVI PILLARISETTY ,  SANSAPTAK DASGUPTA ,  NITI GOEL ,  VAN H. LE ,  MARKO RADOSAVLJEVIC ,  GILBERT DEWEY ,  NILOY MUKHERJEE ,  MATTHEW V. METZ ,  WILLY RACHMADY ,  JACK T. KAVALIEROS ,  BENJAMIN CHU-KUNG ,  HAROLD W. KENNEL ,  STEPHEN M. CEA ,  ROBERT S. CHAU

IPC分类号： H01L29/78 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/165 ,  H01L29/267

CPC分类号： H01L29/785 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823462 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/165 ,  H01L29/20 ,  H01L29/267 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7851

摘要： Ge and III-V channel semiconductor devices having maximized compliance and free surface relaxation and methods of fabricating such Ge and III-V channel semiconductor devices are described. For example, a semiconductor device includes a semiconductor fin disposed above a semiconductor substrate. The semiconductor fin has a central protruding or recessed segment spaced apart from a pair of protruding outer segments along a length of the semiconductor fin. A cladding layer region is disposed on the central protruding or recessed segment of the semiconductor fin. A gate stack is disposed on the cladding layer region. Source/drain regions are disposed in the pair of protruding outer segments of the semiconductor fin.

摘要翻译： 描述了具有最大化顺应性和自由表面弛豫的Ge和III-V沟道半导体器件以及制造这种Ge和III-V沟道半导体器件的方法。 例如，半导体器件包括设置在半导体衬底之上的半导体鳍。 半导体鳍片具有沿着半导体鳍片的长度与一对突出外部部分间隔开的中心突出或凹陷部分。 在半导体翅片的中央突出或凹陷部分上设置包覆层区域。 栅极堆叠设置在包覆层区域上。 源极/漏极区域设置在半导体鳍片的一对突出的外部段中。

公开(公告)号：US20240365513A1

公开(公告)日：2024-10-31

申请号：US18394503

申请日：2023-12-22

申请人： Intel Corporation

发明人： Prabhakar SUBRAHMANYAM ,  Ying-Feng PANG ,  Vishnu Prasadh SUGUMAR

IPC分类号： H05K7/20 ,  F25B5/02 ,  F25B49/02 ,  G06F1/20

CPC分类号： H05K7/20381 ,  F25B5/02 ,  F25B49/022 ,  G06F1/206 ,  H05K7/20309 ,  H05K7/20327 ,  F25B2700/191 ,  F25B2700/197 ,  F25B2700/2108 ,  F25B2700/21174 ,  F25B2700/21175

摘要： An apparatus and method for cooling a computing system, comprising a plurality of electronic components, with a cooling system. The cooling system includes a closed loop for the two-phase coolant, wherein the two-phase coolant has a saturation temperature. The closed loop includes a valve fluidly connected between an outlet of a heat exchanger and an inlet of a plurality of evaporator structures configured to be thermally coupled to the plurality of electronic components, and a compressor fluidly connected between an outlet of the plurality of evaporator structures and an inlet of the heat exchanger. The apparatus and method for the cooling system are configured to monitor one or more system temperatures of the computing system and adjust an operation of at least one of the valve or the compressor to alter the saturation temperature based on the one or more system temperatures.

公开(公告)号：US20240365322A1

公开(公告)日：2024-10-31

申请号：US18571718

申请日：2022-08-03

申请人： INTEL CORPORATION

发明人： Toufiqul ISLAM ,  Debdeep CHATTERJEE ,  Sergey PANTELEEV ,  Salvatore TALARICO

IPC分类号： H04W72/20 ,  H04W72/563

CPC分类号： H04W72/20 ,  H04W72/563

摘要： This disclosure describes systems, methods, and devices related to multiplexing uplink transmissions. A user equipment (UE) device may detect a first set of beta offset indices associated with multiplexing high priority uplink control information (UCI) into a physical uplink shared control channel (PUSCH); detect a second set of beta offset indices associated multiplexing low priority UCI into the PUSCH; detect downlink control information (DCI) using a physical downlink control channel (PDCCH) which schedules the PUSCH; determine, based on the first set of beta offset indices and the second set of beta offset indices, that UE device is to multiplex the high priority UCI with the low priority UCI into the PUSCH; and encode, based on the second set of beta offset indices, a multiplexed uplink transmission for transmission to the 5G network device using the PUSCH, the multiplexed uplink transmission comprising the high priority UCI and the low priority UCI.

公开(公告)号：US20240364641A1

公开(公告)日：2024-10-31

申请号：US18768909

申请日：2024-07-10

申请人： Intel Corporation

发明人： Patrick CONNOR ,  James R. HEARN ,  Kevin LIEDTKE ,  Scott P. DUBAL

IPC分类号： H04L49/356 ,  G06F9/455 ,  H04L47/125 ,  H04L47/32 ,  H04L67/1097 ,  H04L69/22

CPC分类号： H04L49/356 ,  G06F9/45558 ,  H04L47/125 ,  H04L47/32 ,  H04L67/1097 ,  H04L69/22 ,  G06F2009/4557 ,  G06F2009/45583 ,  G06F2009/45595

摘要： Examples described herein relate to a switch device for a rack of two or more physical servers, wherein the switch device is coupled to the two or more physical servers and the switch device performs packet protocol processing termination for received packets and provides payload data from the received packets without a received packet header to a destination buffer of a destination physical server in the rack. In some examples, the switch device comprises at least one central processing unit, the at least one central processing unit is to execute packet processing operations on the received packets. In some examples, a physical server executes at least one virtualized execution environments (VEE) and the at least one central processing unit executes a VEE for packet processing of packets with data to be accessed by the physical server that executes the VEE.