公开(公告)号：US10224256B2

公开(公告)日：2019-03-05

申请号：US15625464

申请日：2017-06-16

Applicant: J-DEVICES CORPORATION

Inventor： Hirokazu Machida ,  Kazuhiko Kitano

IPC: H01L21/48 ,  H01L23/14 ,  H01L21/56 ,  H01L23/31 ,  H01L23/544 ,  H01L23/552 ,  H01L23/00 ,  H01L23/538 ,  H01L23/498

Abstract: A manufacturing method of a semiconductor package includes etching a first surface and a side surface of a base substrate, the base substrate including the first, a second and the side surfaces positioned between the first and the second surfaces, the base substrate containing a metal, attaching a metal different from the metal contained in the base substrate to the first and the side surfaces, disposing a semiconductor device on the second surface, the semiconductor device having an external terminal, forming a resin insulating layer sealing the semiconductor device, forming a first conductive layer on the resin insulating layer, forming an opening, exposing the external terminal, in the first conductive layer and the resin insulating layer; and forming a metal layer on the first and the side surfaces, on the first conductive layer and in the opening.

公开(公告)号：US09635762B2

公开(公告)日：2017-04-25

申请号：US14803889

申请日：2015-07-20

Applicant: J-DEVICES CORPORATION

Inventor： Shinji Watanabe ,  Sumikazu Hosoyamada ,  Shingo Nakamura ,  Hiroshi Demachi ,  Takeshi Miyakoshi ,  Tomoshige Chikai ,  Kiminori Ishido ,  Hiroaki Matsubara ,  Takashi Nakamura ,  Hirokazu Honda ,  Yoshikazu Kumagaya ,  Shotaro Sakumoto ,  Toshihiro Iwasaki ,  Michiaki Tamakawa

IPC: H01L23/02 ,  H01L23/10 ,  H05K1/18 ,  H01L23/367 ,  H05K1/02 ,  H01L25/10 ,  H01L23/36 ,  H01L23/373 ,  H01L23/433 ,  H01L23/498 ,  H01L23/31

CPC classification number: H05K1/181 ,  H01L23/3128 ,  H01L23/36 ,  H01L23/3675 ,  H01L23/3677 ,  H01L23/3733 ,  H01L23/4334 ,  H01L23/49816 ,  H01L25/105 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/15331 ,  H01L2924/1815 ,  H05K1/0204 ,  H05K1/0206 ,  H05K1/0209 ,  H05K1/141 ,  H05K2201/0275 ,  H05K2201/066 ,  H05K2201/10515 ,  H05K2203/1311 ,  H05K2203/1322 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A stacked semiconductor package includes a first semiconductor package including a first circuit board and a first semiconductor device mounted on the first circuit board; a second semiconductor package including a second circuit board and a second semiconductor device mounted on the second circuit board, the second semiconductor package being stacked on the first semiconductor package; and a heat transfer member provided on the first semiconductor device and a part of the first circuit board, the part being around the first semiconductor device.

公开(公告)号：US09595488B2

公开(公告)日：2017-03-14

申请号：US15010988

申请日：2016-01-29

Applicant: J-DEVICES CORPORATION

Inventor： Yoshihiro Tanaka

IPC: H01L23/52 ,  H01L29/40 ,  H01L23/48 ,  H01L23/495 ,  H01L23/498 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L23/49513 ,  H01L23/49582 ,  H01L23/49861 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/83 ,  H01L25/50 ,  H01L2224/26175 ,  H01L2224/29011 ,  H01L2224/29014 ,  H01L2224/29015 ,  H01L2224/29078 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48105 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/83048 ,  H01L2224/83192 ,  H01L2224/83385 ,  H01L2224/83439 ,  H01L2224/83815 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2924/181 ,  H01L2924/014 ,  H01L2224/45099 ,  H01L2924/00

Abstract: A semiconductor device according to one embodiment of the present invention includes a semiconductor element, an island having a surface on which the semiconductor element is fixed using a first metal, and a first pattern formed by a second metal, the first pattern being arranged on one part of the surface, wherein the second metal has a greater wetting characteristic than the surface when the first metal is melted.

Abstract translation: 根据本发明的一个实施例的半导体器件包括半导体元件，具有使用第一金属固定半导体元件的表面的岛和由第二金属形成的第一图案，第一图案被布置在一个上 表面的一部分，其中当第一金属熔化时，第二金属具有比表面更大的润湿特性。

公开(公告)号：US09553052B2

公开(公告)日：2017-01-24

申请号：US14963970

申请日：2015-12-09

Applicant: J-DEVICES CORPORATION

Inventor： Hiroaki Matsubara ,  Toshihiro Iwasaki ,  Tomoshige Chikai ,  Kiminori Ishido ,  Shinji Watanabe ,  Michiaki Tamakawa

IPC: H01L29/82 ,  H01L23/552

CPC classification number: H01L23/552 ,  H01L24/19 ,  H01L24/20 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/8203 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/15153 ,  H01L2224/83

Abstract: A magnetic shielding package of a non-volatile magnetic memory element, including: a soft magnetic material support plate 12; a first insulating material layer 13 formed on the support plate; a non-volatile magnetic memory element 11 fixed on the first insulating material layer; a second insulating material layer 14 that encapsulates the memory element and the periphery thereof; in the second insulating material layer, a wiring layer 15, a soft magnetic layer 15b or 25 and a conductive portion 16 connecting an electrode of the circuit surface of the memory element and the wiring layer; and a magnetic shield part 17 containing a soft magnetic material arranged like a wall at a distance from a side surface of the memory element so as to surround the memory element side surface partially or entirely, the magnetic shield part being magnetically connected to the soft magnetic layer.

Abstract translation: 一种非易失性磁存储元件的磁屏蔽封装，包括：软磁材料支撑板12; 形成在支撑板上的第一绝缘材料层13; 固定在第一绝缘材料层上的非易失性磁存储元件11; 封装存储元件及其周边的第二绝缘材料层14; 在第二绝缘材料层中，布线层15，软磁性层15b或25以及连接存储元件的电路表面的电极和布线层的导电部分16; 以及磁屏蔽部17，所述磁屏蔽部17包含与存储元件的侧面隔开一定距离地配置的软磁性材料，以便部分地或全部地包围存储元件侧表面，所述磁屏蔽部磁性地连接到软磁 层。

公开(公告)号：US09196507B1

公开(公告)日：2015-11-24

申请号：US14807193

申请日：2015-07-23

Applicant: Hiroshi Inoue ,  Akio Katsumata ,  Shigenori Sawachi ,  Osamu Yamagata

Inventor： Hiroshi Inoue ,  Akio Katsumata ,  Shigenori Sawachi ,  Osamu Yamagata

IPC: H01L21/00 ,  H01L23/02 ,  H01L21/48 ,  H01L21/82 ,  H01L23/00

CPC classification number: H01L21/486 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/82 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/73 ,  H01L24/83 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A method of manufacturing a semiconductor device having an insulating substrate, a semiconductor element which is mounted on one main surface of the insulating substrate via adhesive, with an element circuit surface of the semiconductor element facing upwards, a first insulating material layer (A) which seals the element circuit surface of the semiconductor element and the insulating substrate peripheral thereto, a first metal thin film wire layer provided on the first insulating material layer (A) and a portion of which is exposed to an external surface, a first insulating material layer (B) provided on the first metal thin film wire layer, a second insulating material layer provided on a main surface of the insulating substrate where the semiconductor element is not mounted, a second metal thin film wire layer provided inside the second insulating material layer.

Abstract translation: 一种制造具有绝缘基板的半导体器件的方法，半导体元件，其通过粘合剂安装在绝缘基板的一个主表面上，半导体元件的元件电路表面朝上，第一绝缘材料层（A），其 密封半导体元件的元件电路表面和周围的绝缘基板，设置在第一绝缘材料层（A）上并且其一部分暴露于外表面的第一金属薄膜线层，第一绝缘材料层 （B），设置在绝缘基板的未安装半导体元件的主表面上的第二绝缘材料层，设置在第二绝缘材料层内部的第二金属薄膜线层。

公开(公告)号：US09147671B2

公开(公告)日：2015-09-29

申请号：US14190885

申请日：2014-02-26

Applicant: Hiroshi Inoue ,  Akio Katsumata ,  Shigenori Sawachi ,  Osamu Yamagata

Inventor： Hiroshi Inoue ,  Akio Katsumata ,  Shigenori Sawachi ,  Osamu Yamagata

IPC: H01L23/02 ,  H01L21/00 ,  H01L25/065 ,  H01L23/538 ,  H01L23/13 ,  H01L21/82 ,  H01L25/00

CPC classification number: H01L21/486 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/82 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/73 ,  H01L24/83 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor device, having an insulating substrate; a semiconductor element which is mounted on one main surface of the insulating substrate via adhesive, with an element circuit surface of the semiconductor element facing upwards; a first insulating material layer which seals the element circuit surface of the semiconductor element and the insulating substrate peripheral thereto; a first metal thin film wire layer which is provided on the first insulating material layer (A) and a portion of which is exposed to an external surface; a first insulating material layer (B) which is provided on the first metal thin film wire layer; a second insulating material layer which is provided on a main surface of the insulating substrate where the semiconductor element is not mounted; and a second metal thin film wire layer which is provided inside the second insulating material layer.

Abstract translation: 一种半导体器件，具有绝缘基板; 半导体元件，其通过粘合剂安装在绝缘基板的一个主表面上，半导体元件的元件电路表面朝上; 第一绝缘材料层，其密封半导体元件的元件电路表面和周边的绝缘基板; 第一金属薄膜线层，其设置在第一绝缘材料层（A）上并且其一部分暴露于外表面; 设置在第一金属薄膜线层上的第一绝缘材料层（B）; 第二绝缘材料层，设置在绝缘基板的未安装半导体元件的主表面上; 以及设置在第二绝缘材料层内部的第二金属薄膜线层。

公开(公告)号：US20120074594A1

公开(公告)日：2012-03-29

申请号：US13075921

申请日：2011-03-30

Applicant: Hisakazu MARUTANI ,  Yasunari Iwami ,  Tomoshige Chikai ,  Tomoko Takahashi ,  Osamu Yamagata ,  Shingo Mitsugi ,  Chunghao Chen

Inventor： Hisakazu MARUTANI ,  Yasunari Iwami ,  Tomoshige Chikai ,  Tomoko Takahashi ,  Osamu Yamagata ,  Shingo Mitsugi ,  Chunghao Chen

IPC: H01L23/48 ,  H01L21/78 ,  H01L21/50

CPC classification number: H01L23/3128 ,  H01L21/561 ,  H01L23/16 ,  H01L23/5389 ,  H01L23/562 ,  H01L24/04 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/82 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/21 ,  H01L2224/2101 ,  H01L2224/215 ,  H01L2224/22 ,  H01L2224/221 ,  H01L2224/24011 ,  H01L2224/24146 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/76155 ,  H01L2224/82101 ,  H01L2224/82102 ,  H01L2224/92244 ,  H01L2225/06524 ,  H01L2225/06548 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/014 ,  H01L2924/351 ,  H01L2924/00

Abstract: A semiconductor device comprising a support plate, a semiconductor element mounted on the support plate and including a circuit element surface having a plurality of first electrodes, a first insulation layer covering the circuit element surface of the semiconductor element, and including a plurality of first apertures exposing the plurality of first electrodes, a second insulation layer covering an upper part of the support plate and side parts of the semiconductor element, and wirings formed on an upper part of the first insulation layer and on an upper part of the second insulation layer, and electrically connected to the corresponding first electrodes.

Abstract translation: 一种半导体器件，包括支撑板，安装在支撑板上并包括具有多个第一电极的电路元件表面的半导体元件，覆盖半导体元件的电路元件表面的第一绝缘层，并且包括多个第一孔 暴露多个第一电极，覆盖支撑板的上部和半导体元件的侧部的第二绝缘层以及形成在第一绝缘层的上部和第二绝缘层的上部上的布线， 并电连接到相应的第一电极。

公开(公告)号：US11488886B2

公开(公告)日：2022-11-01

申请号：US16592213

申请日：2019-10-03

Applicant: J-DEVICES CORPORATION

Inventor： Masao Hirobe

IPC: H01L23/367 ,  H01L23/00 ,  H01L23/10 ,  H01L23/04 ,  H01L23/373

Abstract: There is provided a semiconductor device including a substrate whose surface is made of an insulation material, a semiconductor chip flip-chip connected on the substrate, and a heat sink bonded to the semiconductor chip via a thermal interface material and fixed to the substrate outside the semiconductor chip, in which the heat sink has a protrusion part protruding toward the substrate and bonded to the substrate via a conductive resin between a part bonded to semiconductor chip and a part fixed to the substrate and the heat sink has a stress absorbing part. According to the present invention, the protrusion part of the heat sink is prevented from being peeled off from the substrate at the part where the protrusion part of the heat sink is bonded to the substrate.

公开(公告)号：US10910294B2

公开(公告)日：2021-02-02

申请号：US16431691

申请日：2019-06-04

Applicant: J-Devices Corporation

Inventor： Kenji Nishikawa

IPC: H01L21/00 ,  H01L23/00 ,  H01L23/495 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56

Abstract: A packaged electronic device includes a substrate comprising a die pad and a lead spaced apart from the die. An electronic device is attached to the die pad top side. A conductive clip is connected to the substrate and the electronic device, and the conductive clip comprises a plate portion attached to the device top side with a conductive material, a clip connecting portion connected to the plate portion and the lead, and channels disposed to extend inward from a lower side of the plate portion above the device top side. The conductive material is disposed within the channels. In another example, the plate portion comprises a lower side having a first sloped profile in a first cross-sectional view such that an outer section of the first sloped profile towards a first edge portion of the plate portion is spaced away from the electronic device further than an inner section of the first sloped profile towards a central portion of the plate portion. Other examples and related methods are also disclosed herein.

公开(公告)号：US10559523B2

公开(公告)日：2020-02-11

申请号：US16053965

申请日：2018-08-03

Applicant: J-DEVICES CORPORATION

Inventor： Masafumi Suzuhara

IPC: H01L23/495 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48 ,  H01L23/00

Abstract: A semiconductor package includes a die pad; a plurality of external connection terminals located around the die pad; a semiconductor chip located on a top surface of the die pad and electrically connected with the plurality of external connection terminals; and a sealing member covering the die pad, the plurality of external connection terminals and the semiconductor chip and exposing an outer terminal of each of the plurality of external connection terminals. A side surface of the outer terminal of each of the plurality of external connection terminals includes a first area, and the first area is plated.