Variable gain amplifier and sampler offset calibration without clock recovery

    公开(公告)号:US11627022B2

    公开(公告)日:2023-04-11

    申请号:US17684268

    申请日:2022-03-01

    申请人: Kandou Labs, S.A.

    发明人: Ali Hormati

    摘要: Methods and systems are described for generating a time-varying information signal at an output of a variable gain amplifier (VGA), sampling, using a sampler having a vertical decision threshold associated with a target signal amplitude, the time-varying information signal asynchronously to generate a sequence of decisions from varying sampling instants in sequential signaling intervals, the sequence of decisions comprising (i) positive decisions indicating the time-varying information signal is above the target signal amplitude and (ii) negative decisions indicating the time-varying information signal is below the target signal amplitude, accumulating a ratio of positive decisions to negative decisions, and generating a gain feedback control signal to adjust a gain setting of the VGA responsive to a mismatch of the accumulated ratio with respect to a target ratio.

    HIGH SPEED COMMUNICATIONS SYSTEM
    2.
    发明申请

    公开(公告)号:US20230068176A1

    公开(公告)日:2023-03-02

    申请号:US18049594

    申请日:2022-10-25

    申请人: Kandou Labs, S.A.

    IPC分类号: H04L25/03 H04L1/00 H04L25/49

    摘要: Transmission of baseband and carrier-modulated vector codewords, using a plurality of encoders, each encoder configured to receive information bits and to generate a set of baseband-encoded symbols representing a vector codeword; one or more modulation circuits, each modulation circuit configured to operate on a corresponding set of baseband-encoded symbols, and using a respective unique carrier frequency, to generate a set of carrier-modulated encoded symbols; and, a summation circuit configured to generate a set of wire-specific outputs, each wire-specific output representing a sum of respective symbols of the carrier-modulated encoded symbols and at least one set of baseband-encoded symbols.

    SKEW DETECTION AND CORRECTION FOR ORTHOGONAL DIFFERENTIAL VECTOR SIGNALING CODES

    公开(公告)号:US20220321319A1

    公开(公告)日:2022-10-06

    申请号:US17845641

    申请日:2022-06-21

    申请人: Kandou Labs, S.A.

    发明人: Ali Hormati

    IPC分类号: H04L7/02 H04L7/00

    摘要: Methods and systems are described for receiving a plurality of signals corresponding to symbols of a codeword on a plurality of wires of a multi-wire bus, and responsively generating a plurality of sub-channel outputs using a plurality of multi-input comparators (MICs) connected to the plurality of wires of the multi-wire bus, generating a plurality of wire-specific skew control signals, each wire-specific skew control signal of the plurality of wire-specific skew control signals generated by combining (i) one or more sub-channel specific skew measurement signals associated with corresponding sub-channel outputs undergoing a transition and (ii) a corresponding wire-specific transition delta, and providing the plurality of wire-specific skew control signals to respective wire-skew control elements to adjust wire-specific skew.

    LOW LATENCY COMBINED CLOCK DATA RECOVERY LOGIC NETWORK AND CHARGE PUMP CIRCUIT

    公开(公告)号:US20220216875A1

    公开(公告)日:2022-07-07

    申请号:US17704616

    申请日:2022-03-25

    申请人: Kandou Labs, S.A.

    摘要: Methods and systems are described for obtaining a sequence of data decisions and an error signal generated by one or more samplers operating on a received input signal according to a sampling clock, applying the sequence of data decisions and the error signal to each logic branch of a set of logic branches, and responsively selecting a logic branch from the set of logic branches, the logic branch selected responsive to (i) a detection of a transitional data pattern in the sequence of data decisions and (ii) the error signal, the selected logic branch generating an output current, and providing the output current to a local oscillator controller, the output current sourcing and sinking current to a capacitor through a resistive element to adjust an input voltage of a proportional control circuit relative to a voltage on the capacitor connected to the resistive element.

    Passive multi-input comparator for orthogonal codes on a multi-wire bus

    公开(公告)号:US11159350B2

    公开(公告)日:2021-10-26

    申请号:US16988469

    申请日:2020-08-07

    申请人: Kandou Labs, S.A.

    IPC分类号: H04L25/02

    摘要: Methods and systems are described for receiving a plurality of signals via a plurality of wires of a multi-wire bus, the plurality of signals corresponding to symbols of a codeword of a vector signaling code, generating, using an interconnected resistor network connected to the plurality of wires of the multi-wire bus, a plurality of combinations of the symbols of the codeword of the vector signaling code on a plurality of output nodes, the plurality of output nodes including a plurality of pairs of sub-channel output nodes associated with respective sub-channels of a plurality of sub-channels, and generating a plurality of sub-channel outputs using a plurality of differential transistor pairs, each differential transistor pair of the plurality of differential transistor pairs connected to a respective pair of sub-channel output nodes of the plurality of pairs of sub-channel output nodes.

    Multidrop data transfer
    7.
    发明授权

    公开(公告)号:US10999106B2

    公开(公告)日:2021-05-04

    申请号:US16351226

    申请日:2019-03-12

    申请人: Kandou Labs, S.A.

    摘要: Multi-drop communications channels can have significantly deep notches in their frequency response causing a corresponding limitation of the effective data transmission rate. A special time-ordered coding method is described which results in the emitted spectrum of the data stream transmitted into the channel having a notch at the same frequency as the notch in the channel frequency response, permitting channel receivers to successfully decode the transmitted data stream. The described coding method may be applied at various multiples of the channel notch frequency to support different throughput rates, and may be combined with other coding techniques such as group or vector signaling codes.

    Low power multilevel driver for generating wire signals according to summations of a plurality of weighted analog signal components having wire-specific sub-channel weights

    公开(公告)号:US10929329B2

    公开(公告)日:2021-02-23

    申请号:US16702284

    申请日:2019-12-03

    申请人: Kandou Labs, S.A.

    IPC分类号: G06F13/42 G06F13/40

    摘要: Methods and systems are described for receiving a set of input bits at a plurality of drivers and responsively generating an ensemble of signals, each respective signal of the ensemble of signals generated by receiving a subset of input bits at a respective driver connected to a respective wire of a multi-wire bus, the received subset of bits corresponding to sub-channels associated with the respective wire, generating a plurality of weighted analog signal components, each weighted analog signal component (i) having a corresponding weight and sign selected from a set of wire-specific sub-channel weights associated with the respective wire and (ii) modulated by a corresponding bit of the received subset of bits, and generating the respective signal by forming a summation of the plurality of weighted analog signal components at a common node connected to the respective wire for transmission over the respective wire of the multi-wire bus.

    Quadrature and duty cycle error correction in matrix phase lock loop

    公开(公告)号:US10686584B2

    公开(公告)日:2020-06-16

    申请号:US16268307

    申请日:2019-02-05

    申请人: Kandou Labs, S.A.

    摘要: Generating, at a plurality of delay stages of a local oscillator, a plurality of phases of a local oscillator signal, generating a loop error signal based on a comparison of one or more phases of the local oscillator signal to one or more phases of a received reference clock, generating a plurality of phase-specific quadrature error signals, each phase-specific quadrature error signal associated with a respective phase of the plurality of phases of the local oscillator signal, each phase-specific quadrature error signal based on a comparison of the respective phase to two or more other phases of the local oscillator signal, and adjusting each delay stage according to a corresponding phase-specific quadrature error signal of the plurality of phase-specific quadrature error signals and the loop error signal.

    Multi-ring cross-coupled voltage-controlled oscillator

    公开(公告)号:US10673443B1

    公开(公告)日:2020-06-02

    申请号:US16378459

    申请日:2019-04-08

    申请人: Kandou Labs, S.A.

    摘要: Two rings of a voltage controlled oscillator (VCO) configured to generate a plurality of phases of an oscillator signal, each ring of the two rings comprising three stages of inverters configured to generate a subset of phases of the plurality of phases of the oscillator signal, cross coupled via each stage to a corresponding stage in an other ring of the two rings using inverters to inverse-phase lock the subsets of phases of the plurality of phases of the oscillator signal of the two rings, and configured to receive inputs at each stage from a previous stage in the ring and a feed-forward signal from a successive stage in the other ring of the two rings, and a tail current supply configured to supply the two rings of the VCO with a tail current, the tail current comprising a low-magnitude proportional component and a high-magnitude integral component.