公开(公告)号：US20230139971A1

公开(公告)日：2023-05-04

申请号：US18148060

申请日：2022-12-29

申请人： Kioxia Corporation

发明人： Shinichi KANNO ,  Hironori UCHIKAWA

IPC分类号： H03M13/29 ,  G06F11/10 ,  H03M13/35 ,  G11C29/52 ,  G06F13/16 ,  G06F13/40 ,  H03M13/00

摘要： A semiconductor memory device includes a plurality of detecting code generators configured to generate a plurality of detecting codes to detect errors in a plurality of data items, respectively, a plurality of first correcting code generators configured to generate a plurality of first correcting codes to correct errors in a plurality of first data blocks, respectively, each of the first data blocks containing one of the data items and a corresponding detecting code, a second correcting code generators configured to generate a second correcting code to correct errors in a second data block, the second data block containing the first data blocks, and a semiconductor memory configured to nonvolatilely store the second data block, the first correcting codes, and the second correcting code.

公开(公告)号：US20230139665A1

公开(公告)日：2023-05-04

申请号：US18092158

申请日：2022-12-30

申请人： Kioxia Corporation

发明人： Marie SIA ,  Yoshihisa KOJIMA ,  Suguru NISHIKAWA ,  Riki SUZUKI

IPC分类号： G06F3/06 ,  G11C11/56 ,  G11C16/04 ,  G11C16/26

摘要： A memory system includes a non-volatile memory chip that includes a memory cell array, and a memory controller. The memory controller is configured to perform a read operation on the non-volatile memory chip by instructing the non-volatile memory chip to perform a sensing operation to read data stored in the memory cell array, estimating a time when the read data becomes ready to be transferred from the non-volatile memory chip to the memory controller, and instructing the non-volatile memory chip, after the estimated time, to perform a transfer operation to transfer the read data to the memory controller.

公开(公告)号：US20230135902A1

公开(公告)日：2023-05-04

申请号：US18091303

申请日：2022-12-29

申请人： Kioxia Corporation

发明人： Xu LI

IPC分类号： G11C16/04 ,  H10B43/27 ,  G11C16/26

摘要： A semiconductor memory device includes a first memory string including a first select transistor, a first memory cell, a first select element, a second memory cell, and a second select element in series, a second memory string including a second select transistor, a third memory cell, a third select element, a fourth memory cell, and a fourth select element in series, and a control circuit. The control circuit is configured to set the second select transistor to an on state, and to set the third select element and the fourth select element to an off state, when reading data of the first memory cell.

公开(公告)号：US11641740B2

公开(公告)日：2023-05-02

申请号：US17010181

申请日：2020-09-02

申请人： Kioxia Corporation

发明人： Takamitsu Ochi ,  Shunsuke Kasashima

IPC分类号： H01L27/11582 ,  H01L27/11565 ,  G11C16/04

摘要： A device includes conductor layers and a first pillar, extending through the conductor layers, that includes a first columnar portion, a second columnar portion, and a middle portion between the first and second columnar portions. A diameter of the middle portion is larger than a diameter of the first columnar portion and larger than a diameter of the second columnar portion. The first columnar portion includes a first semiconductor layer and a first charge storage layer. The second columnar portion includes a second semiconductor layer and a second charge storage layer. The middle portion includes a third semiconductor layer. The first and second semiconductor layers are in contact with the third semiconductor layer on a first side and a second side of the third semiconductor layer, respectively. The first charge storage layer is spaced from the second charge storage layer.

公开(公告)号：US20230130044A1

公开(公告)日：2023-04-27

申请号：US18146222

申请日：2022-12-23

申请人： Kioxia Corporation

发明人： Yoshihiro UOZUMI

IPC分类号： H01L23/00 ,  H01L21/50 ,  H01L21/78

摘要： A method for manufacturing a semiconductor device is provided, including: preparing a first chip forming portion having a first semiconductor substrate, first metal pads provided at the substrate and a first circuit electrically connected to at least a part of the pads, and a second chip forming portion having a second semiconductor substrate, second metal pads provided at substrate and a second circuit electrically connected to at least a part of the pads; bonding the first and the second chip forming portions while joining the first and the second pads to form a bonding substrate having a non-bonded region between the first and the second chip forming portions at an outer peripheral portion thereof; and filling an insulating film into the non-bonded region, at least a part of the insulating film containing at least one selected from the group consisting of silicon nitride and nitrogen-containing silicon carbide.

公开(公告)号：US20230129339A1

公开(公告)日：2023-04-27

申请号：US18145979

申请日：2022-12-23

申请人： Kioxia Corporation

发明人： Takahiro TOMIMATSU ,  Shinya ARAI

IPC分类号： H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L23/535 ,  H01L25/00

摘要： According to one embodiment, a semiconductor device includes a first substrate; a first insulating film provided on the first substrate; a first plug provided in the first insulating film; a second substrate provided on the first insulating film; and a first wiring including a first portion and a second portion. The first portion is provided in the second substrate and coupled to the first plug, and the second portion is provided on the second substrate and coupled to a bonding pad.

公开(公告)号：USRE49508E1

公开(公告)日：2023-04-25

申请号：US17087268

申请日：2020-11-02

申请人： Kioxia Corporation

发明人： Shinichi Kanno

IPC分类号： G11C11/34 ,  G11C16/04 ,  H01L27/11524 ,  H01L27/105 ,  G06F3/06 ,  G06F12/02 ,  G06F12/06 ,  G11C16/16

摘要： According to one embodiment, a memory system classifies a plurality of nonvolatile memory dies connected to a plurality of channels, into a plurality of die groups such that each of the plurality of nonvolatile memory dies belongs to only one die group. The memory system performs a data write/read operation for one die group of the plurality of die groups in accordance with an I/O command from a host designating one of a plurality of regions including at least one region corresponding to each die group. The memory system manages a group of free blocks in the nonvolatile memory for each of the plurality of die group by using a plurality of free block pools corresponding to the plurality of die groups.

公开(公告)号：US20230119989A1

公开(公告)日：2023-04-20

申请号：US18084363

申请日：2022-12-19

申请人： Kioxia Corporation

发明人： Kosuke YANAGIDAIRA ,  Hiroshi TSUBOUCHI

IPC分类号： G11C16/26 ,  G11C16/04 ,  G11C16/32 ,  H10B43/27 ,  H10B43/10 ,  G11C16/08

摘要： A semiconductor memory device includes a memory cell connected between a bit line and a source line, a sense amplifier having a first transistor provided between at least two transistors of the sense amplifier and the bit line, and a controller which executes a read operation to read data stored by the memory cell. In the read operation, the controller applies a first voltage to the first transistor and a second voltage to the source line during a first time period, applies a third voltage to the first transistor and a fourth voltage to the source line during a second time period after the first time period, and applies the first voltage to the first transistor and a fifth voltage to the source line during a third time period after the second time period.

公开(公告)号：US11631693B2

公开(公告)日：2023-04-18

申请号：US16993366

申请日：2020-08-14

申请人： Kioxia Corporation

发明人： Takahito Nishimura ,  Genki Kawaguchi ,  Yusuke Okumura

IPC分类号： H01L27/11582 ,  H01L27/11565 ,  H01L27/1157

摘要： According to one embodiment, a semiconductor memory device includes a substrate, insulating members, first conductive layers, first pillars, and second pillars. The substrate includes a first area, a second area, block regions, and a first dummy block region. The insulating members are arranged at respective boundary portions of the block regions and the first dummy block region. The first conductive layers are partitioned by the insulating members. The first pillars penetrates the first conductive layers in a region where the first area and the block regions overlap. The second pillars penetrates at least one of the first conductive layers in a region where the first area and the first dummy block region overlap.

公开(公告)号：US11631463B2

公开(公告)日：2023-04-18

申请号：US17381248

申请日：2021-07-21

申请人： Kioxia Corporation

发明人： Hiroshi Sukegawa ,  Ikuo Magaki ,  Tokumasa Hara ,  Shirou Fujita

IPC分类号： G11C16/04 ,  G11C16/10 ,  G11C16/08 ,  G11C16/34 ,  G06F3/06 ,  H01L27/11582

摘要： A controller controls a memory including first and second strings. The first and second strings configure first and second string groups, respectively. In each string group, a set of memory cell transistors each from each string configures a unit. The controller is configured to: sequentially write, in the first string group, data in first units to which serially-coupled memory cell transistors respectively belong; sequentially write, in the second string group, data in first units to which serially-coupled memory cell transistors respectively belong; and sequentially write, in the first string group, data in second units to which serially-coupled memory cell transistors respectively belong.