公开(公告)号：US20230135869A1

公开(公告)日：2023-05-04

申请号：US17518575

申请日：2021-11-03

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Nung Yen

IPC分类号： G11C11/406

摘要： The invention provides a dynamic random-access memory (DRAM) and an operation method thereof. The DRAM includes a memory cell array, a temperature sensor, and a refresh logic circuit. The temperature sensor senses a temperature of the DRAM. The refresh logic circuit enters a tRFC based on a refresh command issued by a memory controller to perform an automatic refresh operation on at least one memory cell row of the memory cell array. In a temperature-controlled refresh mode, the refresh logic circuit correspondingly adjusts a number of a plurality of tRAS periods in the tRFC according to a temperature sensing result of the temperature sensor. In a fine granularity refresh mode, the refresh logic circuit correspondingly adjusts the number of the tRAS periods in the tRFC according to a granularity specified by the memory controller.

公开(公告)号：US11641735B1

公开(公告)日：2023-05-02

申请号：US17451157

申请日：2021-10-18

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Yu-Ying Lin

IPC分类号： H01L27/108

摘要： A method of manufacturing a memory structure is provided. The method includes forming a first gate structure, a second gate structure, and a plurality of source/drain regions in a substrate, in which the plurality of source/drain regions are disposed on opposite sides of the first gate structure and the second gate structures; performing a dry etching process to form a trench between the first gate structure and the second gate structure; performing a wet etching process to expand the trench, in which the expanded trench has a hexagonal shaped cross section profile; and forming a bit line contact in the expanded trench.

公开(公告)号：US11641734B2

公开(公告)日：2023-05-02

申请号：US17659493

申请日：2022-04-18

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Szu-Yao Chang

IPC分类号： G11C8/14 ,  G11C11/402 ,  H01L49/02

摘要： A method of forming a semiconductor structure includes forming a capacitor on a substrate. A recess is formed in the capacitor. A drain region is formed in the recess. A word line is formed on the drain region. A gate structure is formed on the drain region, and the gate structure is electrically connected to the word line. A first bit line is formed on the gate structure, such that the first bit line servers as a source region.

公开(公告)号：US11641733B2

公开(公告)日：2023-05-02

申请号：US17454042

申请日：2021-11-08

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Chia-Lin Chang

IPC分类号： H10B12/00 ,  H01L21/311 ,  H01L29/78 ,  H01L23/528 ,  H01L49/02

摘要： A semiconductor includes a semiconductor substrate and pillar type capacitors. The semiconductor substrate includes first connecting pads and second connecting pads. The second connecting pads are disposed on the first connecting pads respectively, and the pillar type capacitors are disposed on the second connecting pads respectively. A first ends of the pillar type capacitors are connected to the second connecting pads respectively, and a second ends of the pillar type capacitors area at the opposite side of the first ends. The distance between the first end and the second end of each of the pillar type capacitors is from 1 micrometer to 1.8 micrometer. A manufacturing method is also provided.

公开(公告)号：US20230130975A1

公开(公告)日：2023-04-27

申请号：US17508965

申请日：2021-10-22

申请人： NANYA TECHNOLOGY CORPORATION

发明人： KAI-PO SHANG ,  JUI-HSIU JAO

IPC分类号： H01L23/525 ,  H01L27/06

摘要： A semiconductor device with a fuse component is provided. The semiconductor device includes a substrate having an active region; a fuse dielectric layer disposed in the active region; and a gate metal layer disposed in the active region and surrounded by the fuse dielectric layer. The he gate metal layer is configured to receive a voltage to change a resistivity between the gate metal layer and the active region.

公开(公告)号：US20230128805A1

公开(公告)日：2023-04-27

申请号：US18088675

申请日：2022-12-26

申请人： NANYA TECHNOLOGY CORPORATION

发明人： TSE-YAO HUANG

IPC分类号： H10B12/00

摘要： A method for forming a semiconductor device includes forming a conductive contact over a semiconductor substrate, and forming a first dielectric layer covering the conductive contact. The method also includes partially removing the first dielectric layer to form an opening exposing a top surface of the conductive contact, and forming a bottom electrode covering sidewalls of the opening and the top surface of the conductive contact. The method further includes depositing a second dielectric layer over the bottom electrode using a first process, and depositing dielectric portions over the second dielectric layer and at top corners of the opening using a second process. The first process has a first step coverage, the second process has a second step coverage, and the second step coverage is smaller than the first step coverage. The method includes forming a top electrode covering the second dielectric layer and the dielectric portions.

公开(公告)号：US20230127860A1

公开(公告)日：2023-04-27

申请号：US17510878

申请日：2021-10-26

申请人： NANYA TECHNOLOGY CORPORATION

发明人： TSE-YAO HUANG

IPC分类号： H01L25/18 ,  H01L23/00 ,  H01L23/532 ,  H01L21/768 ,  H01L25/00

摘要： The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a first chip including: a first inter-dielectric layer positioned on a first substrate; a plug structure positioned in the first inter-dielectric layer and electrically coupled to a functional unit of the first chip; a first redistribution layer positioned on the first inter-dielectric layer and distant from the plug structure; a first lower bonding pad positioned on the first redistribution layer; and a second lower bonding pad positioned on the plug structure; and a second chip positioned on the first chip and including: a first upper bonding pad positioned on the first lower bonding pad; a second upper bonding pad positioned on the second lower bonding pad; and a plurality of storage units electrically coupled to the first upper bonding pad and the second upper bonding pad.

公开(公告)号：US20230123652A1

公开(公告)日：2023-04-20

申请号：US17450833

申请日：2021-10-14

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Chao-Wen LAY

IPC分类号： H01L21/768 ,  G11C5/06 ,  H01L23/532 ,  H01L23/528

摘要： A manufacturing method of a semiconductor device includes forming a bitline on a semiconductor structure comprising a conductive feature therein. A spacer is formed adjacent to a sidewall of the bitline, and the spacer has a dielectric contact in a range of about 2 to about 3. A sacrificial layer is formed over the semiconductor structure and covering the spacer. A portion of the sacrificial layer over the bitline is etched to form a first trench to expose a top surface of the bitline. A dielectric layer is formed in the first trench and over the bitline. After forming the dielectric layer, a remaining portion of the sacrificial layer is removed to form a second trench over the semiconductor structure and an outer sidewall of the first spacer is exposed. A contact is formed in the second trench and connected to the conductive feature of the semiconductor structure.

公开(公告)号：US11631656B2

公开(公告)日：2023-04-18

申请号：US17643177

申请日：2021-12-07

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Hsih-Yang Chiu ,  Yi-Jen Lo

IPC分类号： H01L23/48 ,  H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  H01L21/768

摘要： A semiconductor structure includes a first die, a second die, and a first conductive via. The first die includes a first dielectric layer and a first landing pad embedded in the first dielectric layer. The second die includes a second dielectric layer and a second landing pad embedded in the second dielectric layer. The first die is disposed on the second die. The second landing pad has a through-hole. The first conductive via extends from the first landing pad toward the second landing pad and penetrates through the through-hole of the second landing pad.

公开(公告)号：US11631637B2

公开(公告)日：2023-04-18

申请号：US17751948

申请日：2022-05-24

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Tse-Yao Huang

IPC分类号： H01L23/48 ,  H01L23/498 ,  H01L23/00 ,  H01L23/528 ,  H01L21/48

摘要： The present application provides a method for fabricating a semiconductor device including providing a semiconductor substrate, forming a first stress-relieving structure including a first conductive frame above the semiconductor substrate and a plurality of first insulating pillars within the first conductive frame, forming a second stress-relieving structure comprising a plurality of second conductive pillars above the first stress-relieving structure and a second insulating frame, the plurality of second conductive pillars are disposed within the second conductive frame, wherein the plurality of second conductive pillars is disposed correspondingly above the plurality of first insulating pillars, and the second insulating frame is disposed correspondingly above the first conductive frame; and forming a conductive structure including a supporting portion above the second stress-relieving structure, a conductive portion adjacent to the supporting portion, and a plurality of spacers attached to two sides of the conductive portion.