-
1.发明公开公开(公告)号：US20240029765A1
公开(公告)日：2024-01-25
申请号：US18375968
申请日：2023-10-02
申请人： Nantero, Inc.
发明人： Takao Akaogi , Jia Luo , Nancy See Loiu Leong
CPC分类号： G11C7/065 , G11C7/20 , G11C7/1057 , G11C7/1084 , G11C16/12 , G11C16/0441
摘要： The present disclosure generally relates to circuit architectures for programming and accessing resistive change elements. The circuit architectures can program and access resistive change elements using neutral voltage conditions. The present disclosure also relates to methods for programming and accessing resistive change elements using neutral voltage conditions. The present disclosure additionally relates to sense amplifiers configurable into initializing configurations for initializing the sense amplifiers and comparing configurations for comparing voltages received by the sense amplifiers. The sense amplifiers can be included in the circuit architectures of the present disclosure.
-
公开(公告)号：US20240013834A1
公开(公告)日：2024-01-11
申请号：US18370541
申请日：2023-09-20
申请人： Nantero, Inc.
发明人： Claude L. Bertin
CPC分类号： G11C13/025 , H10K10/50 , H10K19/202 , H10K85/221
摘要： The present disclosure generally relates to multi-switch storage cells (MSSCs), three-dimensional MSSC arrays, and three-dimensional MSSC memory. Multi-switch storage cells include a cell select device, multiple resistive change elements, and an intracell wiring electrically connecting the multiple resistive change elements together and to the cell select device. MSSC arrays are designed (architected) and operated to prevent inter-cell (sneak path) currents between multi-switch storage cells, which prevents stored data disturb from adjacent cells and adjacent cell data pattern sensitivity. Additionally, READ and WRITE operations may be performed on one of the multiple resistive change elements in a multi-switch storage cell without disturbing the stored data in the remaining resistive change elements. However, controlled parasitic currents may flow in the remaining resistive change elements within the cell. Isolating each multi-switch storage cell in a three-dimensional MSSC array, enables in-memory computing for applications such as data processing for machine learning and artificial intelligence.
-
公开(公告)号：US11798623B2
公开(公告)日：2023-10-24
申请号：US17519828
申请日：2021-11-05
申请人： Nantero, Inc.
发明人： Claude L. Bertin
CPC分类号： G11C13/025 , H10K10/50 , H10K19/202 , H10K85/221
摘要： The present disclosure generally relates to multi-switch storage cells (MSSCs), three-dimensional MSSC arrays, and three-dimensional MSSC memory. Multi-switch storage cells include a cell select device, multiple resistive change elements, and an intracell wiring electrically connecting the multiple resistive change elements together and to the cell select device. MSSC arrays are designed (architected) and operated to prevent inter-cell (sneak path) currents between multi-switch storage cells, which prevents stored data disturb from adjacent cells and adjacent cell data pattern sensitivity. Additionally, READ and WRITE operations may be performed on one of the multiple resistive change elements in a multi-switch storage cell without disturbing the stored data in the remaining resistive change elements. However, controlled parasitic currents may flow in the remaining resistive change elements within the cell. Isolating each multi-switch storage cell in a three-dimensional MSSC array, enables in-memory computing for applications such as data processing for machine learning and artificial intelligence.
-
公开(公告)号：US11258023B1
公开(公告)日：2022-02-22
申请号：US16985657
申请日：2020-08-05
发明人： Mark Ramsbey , Thomas Rueckes , Tatsuya Yamaguchi , Syuji Nozawa , Nagisa Sato
IPC分类号： H01L21/764 , H01L51/10 , H01L51/00 , H01L27/28 , H01L51/05
摘要： A method to fabricate a resistive change element. The method may include forming a stack over a substrate. The stack may include a conductive material, a resistive change material, a first surface, and a second surfaces opposite the first surface. The method may further include depositing a first material over the stack such that the first material directly contacts at least one of the first surface and the second surface of the stack. The method may also include after depositing the first material, forming a second material over the first material and evaporating a portion of the first material through the second material to create a gap between the second material and the at least one of the first surface and the second surface of the stack.
-
公开(公告)号：US20210188644A1
公开(公告)日：2021-06-24
申请号：US16722779
申请日：2019-12-20
申请人： Nantero, Inc.
IPC分类号： C01B32/166 , B82Y40/00 , D01F9/127
摘要： Methods for making porous nanotube fabrics are disclosed. Within the methods of the present disclosure, a porogen-loaded nanotube application solution is formed by combining a first volume of nanotube elements with a second volume of fuel material in a liquid medium to form a porogen-loaded nanotube application solution. In some aspects of the present disclosure, a third volume of oxidizer material is also combined into the liquid medium. A porogen-loaded nanotube fabric is formed by depositing the porogen-loaded nanotube application solution. In some aspects of the present disclosure, the fuel material within the porogen-loaded nanotube application solution will react with oxidizer material when heat is applied to a sufficient degree and volatize. The off-gassed fuel material will then leave behind voids in the nanotube fabric, rendering the fabric porous.
-
公开(公告)号：US10714537B2
公开(公告)日：2020-07-14
申请号：US16005011
申请日：2018-06-11
申请人： Nantero, Inc.
发明人： Claude L. Bertin
IPC分类号： H01L27/28 , B82Y10/00 , H01L51/00 , H03K19/20 , G06F30/30 , H01L21/02 , H01L29/16 , H01L29/78 , H01L51/10 , H01L51/05 , B82Y40/00
摘要： Inverter circuits and NAND circuits comprising nanotube based FETs and methods of making the same are described. Such circuits can be fabricating using field effect transistors comprising a source, a drain, a channel region, and a gate, wherein the first channel region includes a fabric of semiconducting nanotubes of a given conductivity type. Such FETs can be arranged to provide inverter circuits in either two-dimension or three-dimensional (stacked) layouts. Design equations based upon consideration of the electrical characteristics of the nanotubes are described which permit optimization of circuit design layout based upon constants that are indicative of the current carrying capacity of the nanotube fabrics of different FETs.
-
公开(公告)号：US20200161304A1
公开(公告)日：2020-05-21
申请号：US16752861
申请日：2020-01-27
申请人： Nantero, Inc.
发明人： Claude L. BERTIN , Thomas RUECKES , X.M. Henry HUANG , Ramesh SIVARAJAN , Eliodor G. Ghenciu , Steven L. KONSEK , Mitchell MEINHOLD
IPC分类号： H01L27/102 , G11C13/02 , B82Y10/00
摘要： Under one aspect, a non-volatile nanotube diode device includes first and second terminals; a semiconductor element including a cathode and an anode, and capable of forming a conductive pathway between the cathode and anode in response to electrical stimulus applied to the first conductive terminal; and a nanotube switching element including a nanotube fabric article in electrical communication with the semiconductive element, the nanotube fabric article disposed between and capable of forming a conductive pathway between the semiconductor element and the second terminal, wherein electrical stimuli on the first and second terminals causes a plurality of logic states.
-
公开(公告)号：US20200098429A1
公开(公告)日：2020-03-26
申请号：US16600025
申请日：2019-10-11
申请人： Nantero, Inc.
发明人： Jia Luo , Sheyang Ning , Lee E. Cleveland
IPC分类号： G11C13/00
摘要： Devices and methods for programming resistive change elements using an electrical stimulus are disclosed. According to some aspects of the present disclosure the devices and methods program at least one resistive change element within at least one resistive change element cell in a resistive change element array using an electrical stimulus having a voltage level greater than a steady state voltage level that can be supplied by a power supply.
-
公开(公告)号：US20190341550A1
公开(公告)日：2019-11-07
申请号：US16510952
申请日：2019-07-14
申请人： Nantero, Inc.
摘要： Methods for scaling dimensions of resistive change elements, resistive change element arrays of scalable resistive change elements, and sealed resistive change elements are disclosed. According to some aspects of the present disclosure the methods for scaling dimensions of resistive change elements and the resistive change element arrays of scalable resistive change elements reduce the impact of overlapping materials on the switching characteristics of resistive change elements. According to some aspects of the present disclosure the methods for scaling dimensions of resistive change elements include sealing surfaces of resistive change elements. According to some aspects of the present disclosure the methods for scaling dimensions of resistive change elements include forming barriers to copper migration in a copper back end of the line.
-
公开(公告)号：US10355206B2
公开(公告)日：2019-07-16
申请号：US15486032
申请日：2017-04-12
申请人： Nantero, Inc.
摘要： Methods for scaling dimensions of resistive change elements, resistive change element arrays of scalable resistive change elements, and sealed resistive change elements are disclosed. According to some aspects of the present disclosure the methods for scaling dimensions of resistive change elements and the resistive change element arrays of scalable resistive change elements reduce the impact of overlapping materials on the switching characteristics of resistive change elements. According to some aspects of the present disclosure the methods for scaling dimensions of resistive change elements include sealing surfaces of resistive change elements. According to some aspects of the present disclosure the methods for scaling dimensions of resistive change elements include forming barriers to copper migration in a copper back end of the line.
-
-
-
-
-
-
-
-
-
搜索结果
436 条记录 (耗时 0.024 秒)
