公开(公告)号：US20050228629A1

公开(公告)日：2005-10-13

申请号：US10505260

申请日：2002-02-22

申请人： Damian Dalton

发明人： Damian Dalton

IPC分类号： G06F17/50

CPC分类号： G06F17/5022

摘要： A method and a processor for parallel processing of logic event simulation on circuits comprising a polarity of logic gates, the logic gates having interconnect lines therebetween, the processor (1) further comprising a main processor (2) and an associative memory mechanism (3), the associative memory mechanism (3) comprising a plurality of associative arrays (5, 6) and at least one result register, and there is provided accessible external memory (4) in which a circuit representation may be stored and divided into a plurality of segments, each of the segments having a segment identifier, which in turn has segment data associated therewith. The segment identifier and segment data being stored in a segment table (14) in the associative memory mechanism. Each of the segments may then be brought into the associative memory mechanism (3) for evaluation one at a time. There is additionally provided an amended result registering mechanism (8) to allow numerous tests and gate pairs to be carried out and recorded.

摘要翻译： 一种用于在包括逻辑门极性的电路上并行处理逻辑事件模拟的方法和处理器，所述逻辑门之间具有互连线，所述处理器还包括主处理器和关联存储器机构， ，所述关联存储器机构（3）包括多个关联阵列（5,6）和至少一个结果寄存器，并且提供可访问的外部存储器（4），其中电路表示可被存储并分成多个 段，每个段具有段标识符，其又具有与其相关联的段数据。 段标识符和段数据被存储在关联存储机构中的段表（14）中。 然后可以将每个段进入关联存储器机构（3），以一次一个地评估。 另外还提​​供了修改结果登记机制（8），以允许执行和记录许多测试和门对。