公开(公告)号：US20050121805A1

公开(公告)日：2005-06-09

申请号：US11035999

申请日：2005-01-18

申请人： Tomoo Matsuzawa ,  Takafumi Nishita ,  Yasuyuki Nakajima ,  Toshiaki Morita

发明人： Tomoo Matsuzawa ,  Takafumi Nishita ,  Yasuyuki Nakajima ,  Toshiaki Morita

IPC分类号： H01L23/48 ,  H01L21/60 ,  H01L23/498 ,  H01L25/065 ,  H01L21/48

CPC分类号： H01L24/85 ,  H01L23/49838 ,  H01L24/05 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/4809 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/48624 ,  H01L2224/48647 ,  H01L2224/49052 ,  H01L2224/49171 ,  H01L2224/49431 ,  H01L2224/49433 ,  H01L2224/73265 ,  H01L2224/85 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01057 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19043 ,  H01L2924/01039 ,  H01L2224/78 ,  H01L2924/00012 ,  H01L2924/00

摘要： A semiconductor device comprising a plurality of wires for electrically connecting a plurality of electrode pads arranged on a main surface of a semiconductor chip along one side of the semiconductor chip to a plurality of connecting portions arranged on the main surface of a wiring substrate along one side of the semiconductor chip, respectively, wherein second wires out of the plural wires consisting of first and second wires adjacent to each other have a larger loop height than the first wires, one end portions of the second wires are connected to the electrode pads at positions farther from one side of the semiconductor chip than the one end portions of the first wires, and the other end portions of the second wires are connected to the connecting portions at positions farther from one side of the semiconductor chip than the other end portions of the first wires.

摘要翻译： 一种半导体器件，包括多个引线，用于将布置在半导体芯片的主表面上的多个电极焊盘沿着半导体芯片的一侧电连接到布置在布线基板的主表面上的多个连接部分 其中，由彼此相邻的第一和第二布线组成的多根导线中的第二布线具有比第一布线更大的环形高度，第二布线的一个端部在电极焊盘的位置处连接 比半导体芯片的一侧比第一布线的一个端部更远，而第二布线的另一个端部在与半导体芯片的另一个端部相比更靠近半导体芯片的一侧的位置处连接到连接部分 第一根电线

公开(公告)号：US07225372B2

公开(公告)日：2007-05-29

申请号：US10949192

申请日：2004-09-27

申请人： Iwao Suzuki ,  Shuji Kikuchi ,  Fumie Kobayashi ,  Hideyuki Aoki

发明人： Iwao Suzuki ,  Shuji Kikuchi ,  Fumie Kobayashi ,  Hideyuki Aoki

IPC分类号： G11C29/00

CPC分类号： G11C29/56 ,  G11C29/10

摘要： A testing circuit using ALPG is mounted in a testing board in which sockets for mounting semiconductor memories as devices to be tested in the board is mounted and a volatile memory for storing a data table for generating a random pattern is provided in the testing circuit so that a test using a test pattern having no regularity is performed using the data table in addition to a test using a test pattern having regularity generated by the ALPG.

摘要翻译： 使用ALPG的测试电路安装在测试板中，其中安装半导体存储器的插座作为板中要测试的器件，并且在测试电路中提供用于存储用于产生随机模式的数据表的易失性存储器，使得 除了使用由ALPG生成的规则性的测试图案的测试之外，还使用数据表来执行使用不规则的测试图案的测试。