公开(公告)号：US20200294582A1

公开(公告)日：2020-09-17

申请号：US16887306

申请日：2020-05-29

Applicant: Toshiba Memory Corporation ,  SanDisk Technologies LLC

Inventor： Tomoharu Tanaka ,  Jian Chen

IPC: G11C11/56 ,  G11C16/04 ,  G11C16/34 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  G11C16/12 ,  G11C16/10

Abstract: A non-volatile semiconductor memory device includes an electrically data rewritable non-volatile semiconductor memory cell and a write circuit for writing data in the memory cell, the write circuit writing a data in the memory cells by supplying a write voltage Vpgm and a write control voltage VBL to the memory cell, continuing the writing of the data in the memory cell by changing the value of the write control voltage VBL in response to an advent of a first write state of the memory cell and inhibiting any operation of writing a data to the memory cell by further changing the value of the write control voltage VBL to Vdd in response to an advent of a second write state of the memory cell.

公开(公告)号：US12225720B2

公开(公告)日：2025-02-11

申请号：US17530861

申请日：2021-11-19

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Ryousuke Itou ,  Akihisa Sai ,  Kenzo Iizuka

IPC: H10B41/27 ,  H01L21/3213 ,  H01L21/768 ,  H10B41/10 ,  H10B43/10 ,  H10B43/27 ,  H01L23/522 ,  H01L23/532

Abstract: A vertically alternating sequence of continuous insulating layers and continuous sacrificial material layers is formed over a substrate, and memory opening fill structures including vertical stacks of memory elements are formed through the vertically alternating sequence. Backside trenches are formed to divide the vertically alternating sequence into a plurality of alternating stacks of insulating layers and sacrificial material layers. Bridge structures are formed within each of the backside trenches. The sacrificial material layers are replaced with electrically conductive layers while the bridge structure are present within the backside trenches.

公开(公告)号：US12211724B2

公开(公告)日：2025-01-28

申请号：US17662758

申请日：2022-05-10

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Michio Ohi ,  Maki Ueda ,  Hiroki Mayumi

IPC: H01L23/544 ,  G02B27/34 ,  G06T7/00 ,  G06T7/66 ,  G06T7/73 ,  H01L21/68 ,  H04N23/56

Abstract: An optical alignment method includes providing an emitted radiation beam which includes a first peak wavelength and a second peak wavelength to a chromatic aberration enhancement component which increases a chromatic aberration of the emitted radiation beam, providing a first incident radiation beam having the first peak wavelength and a second incident radiation beam having the second peak wavelength which is shorter than the first peak wavelength to respective first and second alignment marks located at different vertical levels in a device under test, detecting reflected radiation from the first and second alignment marks, and using the detected reflected radiation for optical alignment of layers in the device under test.

公开(公告)号：US12197783B2

公开(公告)日：2025-01-14

申请号：US17732260

申请日：2022-04-28

Applicant: SanDisk Technologies LLC

Inventor： Hua-Ling Cynthia Hsu ,  Fanglin Zhang

IPC: G06F3/06 ,  G06F13/16

Abstract: A command/address sequence associated with a read/write operation for a memory device that utilizes an existing test data bus in a novel way that obviates the need to utilize an I/O bus for the command/address sequence. As such, the command/address sequence can be performed in parallel with the read/write operations, thereby removing a performance bottleneck that would otherwise be caused by the command and address sequencing. The command/address sequence detects a first enable signal and a data signal on the test data bus and decodes the data signal to obtain at least one of a command latch enable signal and address latch enable signal and at least one of a command code and an address code.

公开(公告)号：US12190969B2

公开(公告)日：2025-01-07

申请号：US17895625

申请日：2022-08-25

Applicant: SanDisk Technologies LLC

Inventor： Ke Zhang ,  Liang Li

IPC: G11C16/06 ,  G11C16/10 ,  G11C16/34

Abstract: A memory apparatus and operating method are provided. The apparatus includes memory cells connected to word lines and disposed in memory holes and configured to retain a threshold voltage. The memory holes are organized in rows grouped in strings and the strings comprise a plurality of blocks which comprise planes. A control means is configured to program the memory cells connected to one of the word lines and associated with one of the strings in each of the plurality of planes and acquire a smart verify programming voltage individually for each of the planes in a smart verify operation. The control means concurrently programs at least some of the memory cells connected to each of the word lines in each of the planes in a program operation using the smart verify programming voltage individually acquired for each of the planes in the smart verify operation.

公开(公告)号：US12185540B2

公开(公告)日：2024-12-31

申请号：US17523447

申请日：2021-11-10

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Michiaki Sano ,  Yusuke Mukae ,  Naoki Takeguchi ,  Yujin Terasawa ,  Tatsuya Hinoue ,  Ramy Nashed Bassely Said

IPC: H10B43/27 ,  H10B41/27

Abstract: A method of forming a three-dimensional memory device includes forming an alternating stack of insulating layers and sacrificial material layers over a substrate, forming a memory opening extending through the alternating stack, forming a sacrificial memory opening fill structure in the memory opening, replacing the sacrificial material layers with electrically conductive layers, removing the sacrificial memory opening fill structure selective to the electrically conductive layers, and forming a memory opening fill structure the memory opening after replacing the sacrificial material layers with electrically conductive layers and after removing the sacrificial memory opening fill structure. The memory opening fill structure includes a memory film and a vertical semiconductor channel.

公开(公告)号：US12160989B2

公开(公告)日：2024-12-03

申请号：US17716698

申请日：2022-04-08

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Ramy Nashed Bassely Said ,  Raghuveer S. Makala ,  Jiahui Yuan ,  Senaka Kanakamedala

IPC: H01L23/48 ,  H01L23/52 ,  H01L23/528 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, memory openings vertically extending through the alternating stack, memory opening fill structures located within a respective one of the memory openings, and a drain-select-level isolation structure. One of the insulating layers is a composite insulating layer including an insulating-material-containing sublayer consisting essentially of an insulating material and an etch stop dielectric material sublayer having a material composition that is different from the insulating material. The etch stop dielectric material sublayer can be employed as an etch stop structure during formation of the drain-select-level isolation structure through drain-select-level electrically conductive layers.

公开(公告)号：US12154635B2

公开(公告)日：2024-11-26

申请号：US17410265

申请日：2021-08-24

Applicant: SanDisk Technologies LLC

Inventor： Yu-Chung Lien ,  Henry Chin ,  Erika Penzo

IPC: G11C16/34 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26

Abstract: A memory device that includes a plurality of memory cells arranged in an array is provided. A control circuitry is configured to program a single bit of data in each memory cell of the plurality of memory cells. The control circuitry is further configured to program a first set of memory cells of the plurality of memory cells using a first programming operation that includes a single programming pulse and no verify pulse and program a second set of memory cells of the plurality of memory cells using a second programming operation that includes at least one programming loop with a programming pulse and a verify pulse.

公开(公告)号：US12148478B2

公开(公告)日：2024-11-19

申请号：US17952846

申请日：2022-09-26

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Masaaki Higashitani ,  Abhijith Prakash ,  Dengtao Zhao

IPC: G11C16/14 ,  G11C16/04 ,  G11C16/34 ,  H01L25/065

Abstract: A non-volatile memory system comprises a plurality of non-volatile memory cells divided into three or more tiers. The memory cells can be programmed, erased and read. In order to achieve uniform erase speed for the three or more tiers, the erase process comprises applying a larger voltage bias to control gates of non-volatile memory cells in the outer tiers than the voltage bias applied to control gates of non-volatile memory cells in one or more inner tiers.

公开(公告)号：US12142315B2

公开(公告)日：2024-11-12

申请号：US17825193

申请日：2022-05-26

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Muhammad Masuduzzaman ,  Jiacen Guo

IPC: G11C11/56 ,  G11C16/04 ,  G11C16/10

Abstract: A method for programming a memory array of a non-volatile memory structure, the memory comprising a population of MLC NAND-type memory cells, wherein the method comprises applying: (1) an inhibit condition to one or more bit lines of the memory array, and (2) a zero voltage condition to one or more bit lines of the memory array such that less than half of the adjacent bit lines of the memory array experience a voltage swing between the inhibit condition and the zero voltage condition.