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    SEMICONDUCTOR APPARATUS
    1.
    发明申请
    SEMICONDUCTOR APPARATUS 有权

    公开(公告)号：US20250070036A1

    公开(公告)日：2025-02-27

    申请号：US18805969

    申请日：2024-08-15

    Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

    Inventor： Kei MURAYAMA

    IPC: H01L23/538

    Abstract: A semiconductor apparatus includes three or more semiconductor devices connected in parallel with each other and an interconnect substrate arranged on the semiconductor devices, wherein the semiconductor devices have respective control electrodes and are switched by a voltage applied to the control electrodes, wherein the interconnect substrate includes an insulating layer and a first interconnect pattern arranged on an opposite side of the insulating layer from the semiconductor devices and connecting the control electrodes of the semiconductor devices, wherein the first interconnect pattern includes a same number of interconnects of equal length as the semiconductor devices, and a voltage input point configured to receive a voltage applied to the control electrodes via the interconnects of equal length, and wherein the control electrodes of the semiconductor devices are connected to the voltage input point only by the interconnects of equal length, which extend in different directions from the voltage input point.

    WIRING SUBSTRATE
    2.
    发明申请
    WIRING SUBSTRATE 有权

    公开(公告)号：US20250062231A1

    公开(公告)日：2025-02-20

    申请号：US18795429

    申请日：2024-08-06

    Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

    Inventor： Takashi NISHIYAMA ,  Yoshiki AKIYAMA

    IPC: H01L23/528 ,  H01L23/532 ,  H01L23/538

    Abstract: A wiring substrate includes a first wiring layer, a first insulating layer, and a second wiring layer. The first insulating layer covers the first wiring layer. The second wiring layer is formed on an upper surface of the first insulating layer and is electrically connected to the first wiring layer. The upper surface of the first insulating layer includes a first roughened surface, and a second roughened surface having a greater roughness than the first roughened surface. The second roughened surface includes a wrinkle pattern resulting from buckling. A volume percent of the first wiring layer located in a first region that overlaps the first roughened surface in plan view is greater than a volume percent of the first wiring layer located in a second region that overlaps the second roughened surface in plan view.

    WIRING BOARD AND SEMICONDUCTOR DEVICE
    3.
    发明申请
    WIRING BOARD AND SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20250054847A1

    公开(公告)日：2025-02-13

    申请号：US18798016

    申请日：2024-08-08

    Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

    Inventor： Kensuke Uchida

    IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00

    Abstract: A wiring board includes an insulating layer and a connection terminal that is formed on a surface of the insulating layer. The connection terminal includes a metal pad that is embedded in the insulating layer and a plated layer that covers an end face of the pad that is exposed on the surface of the insulating layer. The end face of the pad is depressed in a concave surface form to a position lower than the surface of the insulating layer and a surface of the plated layer on a side opposite to a surface making contact with the end face of the pad is depressed in the concave surface form toward the end face.

    Electrostatic chuck and substrate fixing device
    4.
    发明授权
    Electrostatic chuck and substrate fixing device 有权

    公开(公告)号：US12198968B2

    公开(公告)日：2025-01-14

    申请号：US17871237

    申请日：2022-07-22

    Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

    Inventor： Kentaro Kobayashi ,  Mizuki Watanabe ,  Kohei Yamaguchi ,  Atsuo Sato

    IPC: H01L21/683 ,  B28B11/08 ,  C04B37/00 ,  H01J37/32

    Abstract: The electrostatic chuck includes an insulating substrate having a placement surface on which a suction target object is placed and an opposite surface provided on an opposite side to the placement surface; and a gas hole penetrating from the opposite surface to the placement surface. The gas hole has a first hole portion extending from the opposite surface toward the placement surface, a second hole portion extending from the placement surface toward the opposite surface, and a third hole portion provided between the first hole portion and the second hole portion and formed to communicate the first hole portion and the second hole portion each other. The first hole portion is provided not to overlap with the second hole portion in a plan view.

    OPTICAL WAVEGUIDE DEVICE
    5.
    发明申请
    OPTICAL WAVEGUIDE DEVICE 有权

    公开(公告)号：US20240385366A1

    公开(公告)日：2024-11-21

    申请号：US18663665

    申请日：2024-05-14

    Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

    Inventor： Kazunao YAMAMOTO ,  Hisashi KANEDA

    IPC: G02B6/12 ,  G02B6/42

    Abstract: An optical waveguide device includes an interconnect substrate, a first cladding layer disposed on the interconnect substrate, a core layer disposed on the first cladding layer, a second cladding layer disposed on the first cladding layer and selectively covering the core layer, and one or more elevated supports disposed on the first cladding layer and apart from the core layer, wherein one longitudinal-direction end of the core layer and the elevated supports are situated in a component mounting region exposed from the second cladding layer, and wherein the elevated supports are made of a same material as the core layer and have a same thickness as the core layer.

    SEMICONDUCTOR DEVICE
    7.
    发明公开
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20240332109A1

    公开(公告)日：2024-10-03

    申请号：US18612214

    申请日：2024-03-21

    Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

    Inventor： Shinichiro Sekijima

    IPC: H01L23/31 ,  H01L23/00

    CPC classification number: H01L23/3185 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2924/18161 ,  H01L2924/3512

    Abstract: A semiconductor device includes a wiring substrate, a semiconductor chip, and a sealing resin. The semiconductor chip is mounted on the wiring substrate. The sealing resin is filled in a gap between the wiring substrate and the semiconductor chip and extends to an upper surface of the semiconductor chip. The semiconductor chip includes a groove that is formed in an outer peripheral area that is located around a circumference of a predetermined area disposed on the upper surface of the semiconductor chip and that includes a peripheral edge of the upper surface of the semiconductor chip, and that captures an extending portion of the sealing resin extends.

    WAVEGUIDE SUBSTRATE AND METHOD OF MAKING WAVEGUIDE SUBSTRATE
    10.
    发明公开
    WAVEGUIDE SUBSTRATE AND METHOD OF MAKING WAVEGUIDE SUBSTRATE 审中-公开

    公开(公告)号：US20240283121A1

    公开(公告)日：2024-08-22

    申请号：US18436391

    申请日：2024-02-08

    Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

    Inventor： Hiroshi TANEDA ,  Yoko NAKABAYASHI ,  Noriyoshi SHIMIZU ,  Noritaka KATAGIRI ,  Tatsuki SUMI

    IPC: H01P3/12 ,  H01P11/00

    CPC classification number: H01P3/121 ,  H01P11/002

    Abstract: A waveguide substrate includes a core substrate through which first through holes and second through holes are formed, a first conductive layer covering an inner wall of the first through holes and both sides of the core substrate, a second conductive layer covering an inner wall of the second through holes and both sides of the core substrate, a first filler material filling a space surrounded by the first conductive layer inside the first through holes, a second filler material filling a space surrounded by the second conductive layer inside the second through holes, and third conductive layers disposed on respective sides of the core substrate, the third conductive layers overlapping the first and second through holes in a plan view, and the third conductive layers being electrically connected to the first and second conductive layers, wherein the second conductive layer overlaps the first through holes in the plan view.

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