EMBEDDED MULTIPATH MODEL FOR WIRELESS SYSTEMS

    公开(公告)号:US20250055489A1

    公开(公告)日:2025-02-13

    申请号:US18796832

    申请日:2024-08-07

    Abstract: According to at least one aspect of the present disclosure a multipath system is provided, the system comprising: an input configured to receive an input signal; an output configured to provide an output signal; at least one summing node coupled to the output; and one or more multipath units coupled to the input and to the at least one summing node, the one or more multipath units configured to apply a delay to the input signal and to apply a gain to the input signal using one or more coefficients shaped according to a spectrum.

    Multimode longitudinally coupled surface acoustic wave resonator with modulated pitch

    公开(公告)号:US12224737B2

    公开(公告)日:2025-02-11

    申请号:US17743000

    申请日:2022-05-12

    Abstract: A surface acoustic wave resonator that has at least a first resonant frequency and a second resonant frequency is disclosed. The surface acoustic wave resonator can include an interdigital transducer electrode that is positioned over a piezoelectric layer. The interdigital transducer electrode includes fingers having a first pitch. The surface acoustic wave resonator can also include a first set of reflectors that is positioned over the piezoelectric layer. The first set of reflectors includes a first number of reflectors having a second pitch. The first pitch is greater than the second pitch. The surface acoustic wave resonator can also include a second set of reflectors that is positioned over the piezoelectric layer. The second set of reflectors includes a second number of reflectors having a third pitch. The second number of reflectors is different from the first number of reflectors.

    Isolation communications channel using direct demodulation and data-edge encoding

    公开(公告)号:US12218645B2

    公开(公告)日:2025-02-04

    申请号:US18197407

    申请日:2023-05-15

    Abstract: An apparatus for communicating across an isolation barrier includes a differential pair of input terminals. The apparatus includes a bandpass filter circuit configured to receive a received signal on the differential pair of input terminals and to provide a received differential signal on a differential pair of nodes. The apparatus includes a demodulator directly coupled to the bandpass filter circuit and configured to directly demodulate the received differential signal on the differential pair of nodes to provide a demodulated received signal.

    CONTROL FOR RADIO-FREQUENCY AMPLIFIER

    公开(公告)号:US20250038720A1

    公开(公告)日:2025-01-30

    申请号:US18796267

    申请日:2024-08-06

    Abstract: In some embodiments, an amplifier system can include an amplifier circuit having first and second amplifiers configured to amplify respective first and second portions of an input signal. Each of the first and second amplifiers can include a cascode stage with input and output transistors arranged in a cascode configuration. The amplifier system can further include an envelope tracking bias circuit coupled to the amplifier circuit and configured to provide a bias signal to the output transistor of the cascode stage of at least one of the first and second amplifiers. The amplifier system can further include a supply circuit configured to provide a non-envelope tracking supply voltage to the output transistor of the cascode stage of the at least one of the first and second amplifiers.

    Secondary phase compensation assist for PLL IO delay aligning sync signal to system clock signal

    公开(公告)号:US12200091B2

    公开(公告)日:2025-01-14

    申请号:US18202012

    申请日:2023-05-25

    Inventor: Vivek Sarda

    Abstract: A line card receives a SYNC input signal and a first system clock signal. The line card generates a second system clock signal in a PLL and generates a SYNC output signal by dividing the second system clock signal in a divider circuit. The SYNC output signal is fed back as a SYNC feedback signal. The line card determines determining a closest edge of the first system clock signal to a transition of the SYNC input signal and determines a time difference between the closest edge of the first system clock signal and a transition of the SYNC feedback. The SYNC output signal is adjusted based on the time difference using a coarse adjustment by adjusting a divide ratio of the divider circuit and using a fine adjustment in the PLL based on a residue of a remainder of the time difference not accounted for by the coarse time adjustment.

    Tunable filter with mutually coupled inductors

    公开(公告)号:US12199651B2

    公开(公告)日:2025-01-14

    申请号:US17351886

    申请日:2021-06-18

    Abstract: Aspects of this disclosure relate to a tunable filter with tunable rejection. The tunable filter includes mutually coupled inductors and a tunable impedance circuit electrically connected to at least one of the mutually coupled inductors. The tunable impedance circuit is configured to adjust at least two notches in a frequency response of the tunable filter by changing a state of a switch. The tunable filter can filter a radio frequency signal. Related methods, radio frequency systems, radio frequency modules, and wireless communication devices are also disclosed.

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