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    PACKAGE CARRIER AND PACKAGE STRUCTURE
    1.
    发明申请
    PACKAGE CARRIER AND PACKAGE STRUCTURE 有权

    公开(公告)号：US20230068160A1

    公开(公告)日：2023-03-02

    申请号：US17742414

    申请日：2022-05-12

    Applicant: Subtron Technology Co., Ltd.

    Inventor： Shaw-Wen Lao ,  Chih-Peng Fan ,  Ping-I Cheng

    IPC: H01L23/498 ,  H01L25/065 ,  H01L23/538

    Abstract: A package carrier including a multi-layer circuit substrate and a silicon wafer is provided. The multi-layer circuit substrate has a first opening and a second opening communicating with each other. A first diameter and a first depth of the first opening are respectively greater than a second diameter and a second depth of the second opening. The silicon wafer is embedded in the first opening of the multi-layer circuit substrate. The silicon wafer has an active surface and includes a connecting circuit layer. The connecting circuit layer is disposed on the active surface and electrically connected to the multi-layer circuit substrate. The second opening of the multi-layer circuit substrate exposes part of the connecting circuit layer.

    WAVEGUIDE STRUCTURE
    2.
    发明申请
    WAVEGUIDE STRUCTURE 有权

    公开(公告)号：US20210384618A1

    公开(公告)日：2021-12-09

    申请号：US17152800

    申请日：2021-01-20

    Applicant: Subtron Technology Co., Ltd.

    Inventor： Jenn-Hwan Tarng ,  Nai-Chen Liu ,  Yin-Kai Lin ,  Tsung-Han Lee ,  Chao-Wei Chang

    IPC: H01Q1/38 ,  H01Q1/50 ,  H01P1/207 ,  H01P3/12

    Abstract: A waveguide structure includes a dielectric layer, a plurality of circuit layers, a plurality of insulation layers, and a conductor connection layer. The dielectric layer has an opening. The circuit layers are disposed on the dielectric layer. The insulation layers and the circuit layers are alternately stacked. The conductor connection layer covers an outer wall of the opening in a direction perpendicular to the circuit layers and connects at least two circuit layers on two opposite sides of the opening. At least the conductor connection layer and a part of the circuit layers define an air cavity for transmitting signals at a position corresponding to the opening.

    Manufacturing method of package carrier
    3.
    发明授权
    Manufacturing method of package carrier 有权

    公开(公告)号：US10177067B2

    公开(公告)日：2019-01-08

    申请号：US15598324

    申请日：2017-05-18

    Applicant: Subtron Technology Co., Ltd.

    Inventor： Chin-Sheng Wang ,  Chih-Hsien Cheng ,  Shih-Hao Sun

    IPC: H01L21/48 ,  H01L23/00 ,  H01L23/367 ,  H01L23/498

    Abstract: A manufacturing method including following steps is provided. A substrate that includes a core layer, a first conductive layer, and a second conductive layer is provided. A heat conducting channel is formed in the substrate, and an adhesion layer is formed on the second conductive layer to cover a side of the heat conducting channel. A heat conducting element and a buffer layer are placed into the heat conducting channel, and a gap is formed between either the heat conducting element or the buffer layer and an inner side surface of the heat conducting channel. The gap is filled with a first insulant material, and the adhesion layer and the buffer layer are removed to form a cavity and expose the heat conducting element. The first conductive layer and the second conductive layer are patterned to form a first patterned circuit layer and a second patterned circuit layer, respectively.

    Package substrate and manufacturing method thereof
    4.
    发明授权
    Package substrate and manufacturing method thereof 有权

    公开(公告)号：US10123413B2

    公开(公告)日：2018-11-06

    申请号：US15594673

    申请日：2017-05-15

    Applicant: Subtron Technology Co., Ltd.

    Inventor： Chih-Hong Chuang ,  Chien-Hung Wu

    IPC: H05K3/00 ,  H01K1/00 ,  H05K1/09 ,  H01L23/498 ,  H01L21/48 ,  H01L21/683 ,  H05K3/46 ,  H05K1/02 ,  H05K1/11 ,  H05K3/18 ,  H05K3/40 ,  H05K3/20 ,  H05K3/42

    Abstract: A temporary package substrate includes a first copper layer, a second copper layer, a third copper layer, a first plating copper layer, a second plating copper layer, a third plating copper layer, a first dielectric layer, a second dielectric layer and two circuit structures. The second copper layer is located between the first and the third copper layers, and edges of the second copper layer are retracted a distance compared to edges of the first copper layer and edges of the third copper layer. The first and the second dielectric layers completely encapsulate the edges of the second copper layer and the edges of the second plating copper layer. Each of the circuit structures includes at least two patterned circuit layers, an insulation layer located between the patterned circuit layers, and a plurality of conductive through hole structures penetrating the insulation layer and electrically connected with the patterned circuit layers.

    Package carrier and manufacturing method thereof
    7.
    发明授权
    Package carrier and manufacturing method thereof 有权
    包装载体及其制造方法

    公开(公告)号：US09578750B2

    公开(公告)日：2017-02-21

    申请号：US14097269

    申请日：2013-12-05

    Applicant: Subtron Technology Co., Ltd.

    Inventor： Shih-Hao Sun

    IPC: H05K3/00 ,  H05K1/18 ,  H05K3/46

    CPC classification number: H05K3/0097 ,  H01L2224/48091 ,  H01L2224/48472 ,  H01L2924/15311 ,  H05K1/186 ,  H05K3/4602 ,  H05K3/4682 ,  H05K2203/1536 ,  H01L2924/00014 ,  H01L2924/00

    Abstract: A manufacturing of a package carrier includes the following steps. Two base metal layers are bonded together. Two supporting layers are laminated onto the base metal layers respectively. Two release metal films are disposed on the supporting layers respectively. Each release metal film includes a first metal film and a second metal film separable from each other. Two first patterned metal layers are formed on the release metal films respectively. Each first patterned metal layer includes a pad pattern. Two dielectric layers are formed on the release metal films respectively and cover the corresponding first patterned metal layers. Each dielectric layer has a conductive via connecting to the corresponding pad pattern. Two second patterned metal layers are formed on the dielectric layers respectively. Each second patterned metal layer at least covers the conductive via. The base metal layers are separated from each other to form two independent package carriers.

    Abstract translation: 包装载体的制造包括以下步骤。 两个贱金属层结合在一起。 两个支撑层分别层压到基底金属层上。 两个释放金属膜分别设置在支撑层上。 每个释放金属膜包括可彼此分离的第一金属膜和第二金属膜。 分别在剥离金属膜上形成两个第一图案化金属层。 每个第一图案化金属层包括焊盘图案。 分别在剥离金属膜上形成两个电介质层并覆盖对应的第一图案化金属层。 每个电介质层具有连接到相应的焊盘图案的导电通孔。 在介电层上分别形成两个第二图案化金属层。 每个第二图案化金属层至少覆盖导电通孔。 基底金属层彼此分离以形成两个独立的封装载体。

    Manufacturing method of cover structure
    8.
    发明授权
    Manufacturing method of cover structure 有权
    盖结构的制造方法

    公开(公告)号：US09491894B2

    公开(公告)日：2016-11-08

    申请号：US14253883

    申请日：2014-04-16

    Applicant: Chien-Ming Chen

    Inventor： Chien-Ming Chen

    IPC: H05K9/00

    CPC classification number: H05K9/0084 ,  H05K9/0086 ,  Y10T156/10 ,  Y10T156/1039

    Abstract: A method of manufacturing a cover structure is provided. A first insulating layer is provided. The first insulating layer has a first surface and a second surface opposite to each other. A second insulating layer is provided. The second insulating layer has a third surface and a fourth surface opposite to each other and an opening passing through the third surface and the fourth surface. A thickness of the second insulating layer is greater than a thickness of the first insulating layer. The first insulating layer and the second insulating layer are laminated to each other, so that the third surface of the second insulating layer connects to the second surface of the first insulating layer. A cavity is defined by the opening of the second insulating layer and the first insulating layer. A metal layer is formed on the cavity.

    Abstract translation: 提供一种制造盖结构的方法。 提供第一绝缘层。 第一绝缘层具有彼此相对的第一表面和第二表面。 提供第二绝缘层。 第二绝缘层具有彼此相对的第三表面和第四表面以及通过第三表面和第四表面的开口。 第二绝缘层的厚度大于第一绝缘层的厚度。 第一绝缘层和第二绝缘层彼此层叠，使得第二绝缘层的第三表面连接到第一绝缘层的第二表面。 空腔由第二绝缘层和第一绝缘层的开口限定。 在空腔上形成金属层。

    Package structure and manufacturing method thereof
    9.
    发明授权
    Package structure and manufacturing method thereof 有权
    包装结构及其制造方法

    公开(公告)号：US09418931B2

    公开(公告)日：2016-08-16

    申请号：US14675761

    申请日：2015-04-01

    Applicant: Subtron Technology Co., Ltd.

    Inventor： Chien-Ming Chen

    IPC: H01L23/52 ,  H01L23/522 ,  H01L21/768 ,  H01L21/56 ,  H01L23/29

    CPC classification number: H01L23/5226 ,  H01L21/486 ,  H01L21/56 ,  H01L21/568 ,  H01L21/76877 ,  H01L23/293 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/04105 ,  H01L2224/8203 ,  H05K1/185 ,  H05K3/4644 ,  H05K3/4697

    Abstract: A manufacturing method of a package structure includes the following steps. A substrate including a core layer, first and second patterned metal layers is provided. The first and second patterned metal layers are respectively disposed on two opposite surfaces of the core layer. A through cavity penetrating the substrate is formed. The substrate is disposed on a tape carrier. A semiconductor component is disposed in the through cavity. An inner wall of the through cavity and a side surface of the semiconductor component define a groove. The filling compound is dispensed above the groove. A heating process is performed for the filling compound to flow toward the tape carrier and comprehensively fill the groove. First and second stacked layers are respectively laminated onto the first and second patterned metal layers and cover at least a part of the semiconductor component.

    Abstract translation: 包装结构的制造方法包括以下步骤。 提供了包括芯层，第一和第二图案化金属层的衬底。 第一和第二图案化金属层分别设置在芯层的两个相对表面上。 形成穿透基板的通孔。 基板设置在带状载体上。 半导体部件设置在通孔中。 通孔的内壁和半导体部件的侧表面限定凹槽。 填充化合物被分配在凹槽上方。 进行加热处理以使填充化合物朝着带状载体流动，并且全面地填充凹槽。 第一和第二堆叠层分别层压到第一和第二图案化金属层上并覆盖半导体部件的至少一部分。

    SUBSTRATE STRUCTURE AND METHOD OF MANUIFACTURING THE SAME
    10.
    发明申请
    SUBSTRATE STRUCTURE AND METHOD OF MANUIFACTURING THE SAME 审中-公开
    基板结构及其制造方法

    公开(公告)号：US20160050761A1

    公开(公告)日：2016-02-18

    申请号：US14535301

    申请日：2014-11-06

    Applicant: Tzyy-Jang Tseng ,  Chien-Nan Wu

    Inventor： Tzyy-Jang Tseng ,  Chien-Nan Wu

    IPC: H05K3/00 ,  H05K1/02 ,  H05K3/04

    CPC classification number: H05K3/0029 ,  H05K1/0209 ,  H05K3/045 ,  H05K3/28 ,  H05K2201/0376 ,  H05K2201/098 ,  H05K2203/025 ,  H05K2203/072

    Abstract: A method of manufacturing a substrate structure is provided. An insulation substrate having an upper surface is provided. A portion of the upper surface of the insulation substrate is irradiated by a first laser beam so as to form a first intaglio pattern. The first laser beam is IR laser beam or fiber laser beam. The first intaglio pattern has a modification surface. A first metal layer is formed on the upper surface of the insulation substrate, and covers the upper surface of the insulation layer and the modification surface of the first intaglio pattern, and fills up the first intaglio pattern. A grinding process is performed on the first metal layer so as to expose the upper surface of the insulation substrate and define a first patterned circuit layer. A first upper surface of the first patterned circuit layer is aligned with the upper surface of the insulation substrate.

    Abstract translation: 提供一种制造衬底结构的方法。 提供具有上表面的绝缘基板。 绝缘基板的上表面的一部分被第一激光束照射，以形成第一凹版图案。 第一激光束是IR激光束或光纤激光束。 第一个凹版图案具有修饰面。 第一金属层形成在绝缘基板的上表面上，并且覆盖绝缘层的上表面和第一凹版图案的修改表面，并填满第一凹版图案。 在第一金属层上进行研磨处理，以露出绝缘基板的上表面并限定第一图案化电路层。 第一图案化电路层的第一上表面与绝缘基板的上表面对准。

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