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公开(公告)号：US20240364337A1
公开(公告)日：2024-10-31
申请号：US18308100
申请日：2023-04-27
发明人： Weibing Jing , Dan Li
IPC分类号： H03K19/017 , H03K17/06 , H03K17/081
CPC分类号： H03K19/01714 , H03K17/063 , H03K17/08104
摘要： According to some aspects, a circuit, such as an integrated circuit, comprises a bootstrap capacitor terminal, a bootstrap capacitor charging circuit coupled to the bootstrap capacitor terminal; and a bootstrap capacitor charging current limiting circuit coupled to the bootstrap capacitor charging circuit. According to some aspects, the circuit comprises a capacitor terminal, a capacitor charging transistor coupled to the capacitor terminal, a capacitor charging current sensing transistor coupled to the capacitor charging transistor, a current programming transistor coupled to the capacitor charging current sensing transistor; and a capacitor current limiting transistor coupled to the capacitor charging current sensing transistor, to the current programming transistor, and to the capacitor charging transistor. According to some aspects, an apparatus comprises a memory storing instructions to cause a processor to instantiate bootstrap capacitor charging current limiting circuit features.
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公开(公告)号：US20240364323A1
公开(公告)日：2024-10-31
申请号：US18309556
申请日：2023-04-28
IPC分类号： H03K17/16
CPC分类号： H03K17/161
摘要： In some examples, an apparatus includes a first transistor, a second transistor, a third transistor, and a fourth transistor. The first transistor has a source, a gate, and a drain, the drain of the first transistor coupled to a voltage supply terminal. The second transistor has a source, a gate, and a drain, the gate of the second transistor coupled to the gate of the first transistor, and the source of the second transistor coupled to the source of the first transistor. The third transistor has a first terminal and a bulk, the bulk of the third transistor coupled to the drain of the second transistor. The fourth transistor has a first terminal and a bulk, the bulk of the fourth transistor coupled to the drain of the second transistor and the first terminal of the fourth transistor coupled to the first terminal of the third transistor.
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公开(公告)号：US20240364232A1
公开(公告)日：2024-10-31
申请号：US18768245
申请日：2024-07-10
发明人： Michael Lueders , Cetin Kaya , Johan Strydom , Paul Brohlin
摘要： Described embodiments include a rectifier circuit comprising a first resistor with first and second resistor terminals, and a second resistor with third and fourth resistor terminals. The first and third resistor terminals are coupled to an auxiliary power terminal. A current source is coupled between the second resistor terminal and a ground terminal. An amplifier has a first amplifier input coupled to the second resistor terminal, and a second amplifier input coupled to the fourth resistor terminal. A first transistor is coupled between the fourth resistor terminal and a damping terminal, and has a first control terminal coupled to the first amplifier output. A gate drive circuit has an input coupled to the damping terminal. A second transistor is coupled between the damping terminal and a bootstrap supply terminal, and has a second control terminal coupled to an output of the gate drive circuit.
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公开(公告)号：US20240364210A1
公开(公告)日：2024-10-31
申请号：US18309001
申请日：2023-04-28
发明人： Florian Neveu , Stefan Schimonsky , Joerg Kirchner
CPC分类号： H02M1/32 , H02M1/0009 , H02M3/157 , H02M3/1582
摘要： The techniques and circuits, described herein, include solutions for pass-through operation including overcurrent protection in buck-boost converters. In some aspects, first and second switches selectively couple inputs of a peak current comparator to inputs of an error amplifier during pass-through operation. As part of peak current control scheme, one of the peak current comparator inputs is coupled to a current sensor that senses a current through an inductor of the buck-boost converter. As a result, an output of the error amplifier tracks the inductor current during pass-through mode, which may be utilized to implement inductor overcurrent protection in the pass-through mode.
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公开(公告)号：US20240364204A1
公开(公告)日：2024-10-31
申请号：US18308042
申请日：2023-04-27
发明人： Ari Vaananen , Janne Pahkala
CPC分类号： H02M1/0045 , H02M1/0003 , H02M3/158
摘要： A voltage regulator includes a transconductance amplifier having an input and an output. The input is coupled to a voltage regulator output. A droop compensation circuit is coupled to the output of the transconductance amplifier. The droop compensation circuit includes a voltage source circuit configured to cause a voltage at an output of the voltage regulator to change from a first voltage level to a second voltage level in response to a first change in a load condition and remain at the second voltage level until a second change in the load condition. The droop compensation circuit also is configured to cause the voltage at the output of the voltage regulator to change from the second voltage level back to the first voltage level in response to the second change in the load condition.
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公开(公告)号：US20240363691A1
公开(公告)日：2024-10-31
申请号：US18309504
申请日：2023-04-28
发明人： Ebenezer Eshun
IPC分类号： H01L29/10 , H01L21/02 , H01L27/088 , H01L29/06 , H01L29/16 , H01L29/165 , H01L29/20 , H01L29/267 , H01L29/66 , H01L29/78
CPC分类号： H01L29/1095 , H01L21/02529 , H01L21/0254 , H01L21/0262 , H01L27/088 , H01L29/0653 , H01L29/1608 , H01L29/165 , H01L29/2003 , H01L29/267 , H01L29/66681 , H01L29/7816
摘要： The present disclosure generally relates to semiconductor devices including a material having a wide bandgap energy, or simply bandgap, located in a drift well of the semiconductor device. In an example, a semiconductor device includes a laterally-diffused metal-oxide-semiconductor (LDMOS) transistor. The LDMOS transistor includes a drain region, a source region, and a drift well. The drain region is disposed in a semiconductor material of a semiconductor substrate. The source region is disposed in the semiconductor material of the semiconductor substrate. The drift well is disposed laterally between the drain region and the source region. The drift well includes a wide bandgap material, and the wide bandgap material has a bandgap energy that is larger than a bandgap energy of the semiconductor material of the semiconductor substrate.
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公开(公告)号：US20240363434A1
公开(公告)日：2024-10-31
申请号：US18308785
申请日：2023-04-28
发明人： Manoj Mehrotra
IPC分类号： H01L21/8238 , H01L21/02 , H01L27/092 , H01L29/08 , H01L29/165 , H01L29/78
CPC分类号： H01L21/823814 , H01L21/02529 , H01L21/02532 , H01L21/823864 , H01L27/092 , H01L29/0847 , H01L29/165 , H01L29/7848
摘要： Transistors with raised source/drain structures and methods of making the transistors are described. A method for making such transistors includes forming a first gate and a second gate on a substrate, forming a p-doped region adjacent the first gate, and forming an n-doped region adjacent the second gate. The method further includes forming a silicon germanium (SiGe) region in a portion of the p-doped region. Subsequently, the method simultaneously forms raised source-drain structures over the SiGe region and on the n-doped region.
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公开(公告)号：US20240361238A1
公开(公告)日：2024-10-31
申请号：US18309468
申请日：2023-04-28
发明人： Pulak SARANGI , Kaichien TSAI , Boyu SHEN , Anand G. DABAK
IPC分类号： G01N21/53
CPC分类号： G01N21/53 , G01N2201/0698 , G01N2201/1247 , G01N2201/129
摘要： In some examples, a method includes transmitting first light pulses according to a pre-determined pulse pattern in a first measurement period. The method also includes transmitting second light pulses according to the pre-determined pulse pattern in a second measurement period consecutive to the first measurement period, in which at least some of the first and second light pulses being unequally spaced in time across the first and second measurement periods. The method also includes receiving first detection signals representing detection of the first light pulses. The method also includes receiving second detection signals representing detection of the second light pulses. The method also includes providing a first light scattering measurement signal representing the first measurement period responsive to the first detection signals. The method also includes providing a second light scattering measurement signal representing the second measurement period responsive to the second detection signals.
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公开(公告)号：US12132496B2
公开(公告)日：2024-10-29
申请号：US17877956
申请日：2022-07-31
发明人： Luke Goetzke
CPC分类号： H03M1/125 , G06F7/49947 , H03M1/126
摘要： A method and circuit for recovering data from a digital bitstream received from an analog to digital converter includes asynchronously oversampling the digital bitstream at a sampling rate dictated by an estimate of a clock rate of the analog to digital converter and a nominal oversampling factor. The method and circuit also includes calculating widths of bits of the digital bitstream, and calculating a learned oversampling factor using the calculated widths of a predetermined number of bits of the digital bitstream and a minimization function. The method and circuit also includes calculating data bits to be inserted to a digital filter for digestion using the calculated widths of the bits of the digital bitstream and the learned oversampling factor.
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公开(公告)号：US12132488B2
公开(公告)日：2024-10-29
申请号：US18148845
申请日：2022-12-30
发明人： Tolga Dinc , Sachin Kalia , Swaminathan Sankaran
CPC分类号： H03K5/00006 , G06F1/08 , H03H7/0115 , H03H7/0161
摘要： Described embodiments include a circuit having a quadrature phase generator circuit having differential generator inputs, in-phase differential generator outputs and quadrature-phase differential generator outputs. A first frequency multiplier circuit has first differential multiplier inputs and a first multiplier output, wherein the first differential multiplier inputs are coupled to the in-phase differential generator outputs. A second frequency multiplier circuit has second differential multiplier inputs and a second multiplier output. The second multiplier differential inputs are coupled to the quadrature-phase differential generator outputs. A transformer includes a primary inductor and a secondary inductor, wherein the primary inductor is coupled between the first and second multiplier outputs, and the second inductor is coupled between an output voltage terminal and a ground terminal.
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