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公开(公告)号：US20230058135A1
公开(公告)日：2023-02-23
申请号：US17902620
申请日：2022-09-02
发明人： Nozomu HARADA , Kenichi KANAZAWA , Yisuo LI
IPC分类号： H01L27/11
摘要： A method for forming a first impurity region 3 connected to lower portions of first semiconductor pillars and second impurity regions 4a and 4b connected to lower portions of second semiconductor pillars includes forming a semiconductor layer 100 having an impurity concentration lower than an impurity concentration of each of the first impurity region 3 and the second impurity regions 4a and 4b in impurity boundary regions of the first impurity region 3 and the second impurity regions 4a and 4b in a vertical direction and a horizontal direction.
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公开(公告)号：US20220415662A1
公开(公告)日：2022-12-29
申请号：US17902484
申请日：2022-09-02
发明人： Nozomu HARADA
IPC分类号： H01L21/308 , H01L21/02
摘要： A first mask material layer on a Si pillar 7a and a first material layer around a side surface of a top portion of the Si pillar 7a are formed. A second material layer is then formed on an outer periphery of the first material layer. The first mask material layer and the first material layer are then etched by using the second material layer as a mask. A thin SiGe layer, a p+ layer 23a, and a SiO2 layer 24a are then formed in a recessed portion formed around the Si pillar 7a. The exposed side surface of the thin SiGe layer is oxidized to form a SiO2 layer 26a. A TiN layer and a W layer, which are gate conductor layers, are etched by using the SiO2 layers 24a and 26a as masks to form a TiN layer 29a and a W layer 30a. In plan view, the Si pillar 7a, the p+ layer 23a with a small diode junction resistance, and the TiN layer 29a and the W layer 30a, which are gate line conductor layers, thus have a self-alignment relationship, and the p+ layer 23a and the TiN layer 29a are self-aligned with each other with the HfO2 layer 28 and the SiO2 layer 26a therebetween in the vertical direction.
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公开(公告)号：US20220384446A1
公开(公告)日：2022-12-01
申请号：US17840323
申请日：2022-06-14
发明人： Nozomu HARADA , Koji SAKUI
IPC分类号： H01L27/108
摘要： A first impurity layer 101a and a second impurity layer 101b are formed on a substrate Sub at both ends of a Si pillar 100 standing in a vertical direction and having a circular or rectangular horizontal cross-section. Then, a first gate insulating layer 103a and a second gate insulating layer 103b surrounding the Si pillar 100, a first gate conductor layer 104a surrounding the first gate insulating layer 103a, and a second gate conductor layer 104b surrounding the second gate insulating layer 103b are formed. Then, a voltage is applied to the first impurity layer 101a, the second impurity layer 101b, the first gate conductor layer 104a, and the second gate conductor layer 104b to generate an impact ionization phenomenon in a channel region 102 by current flowing between the first impurity layer 101a and the second impurity layer 101b. Of generated electrons and positive holes, the electrons are discharged from the channel region 102 to perform a memory write operation for holding some of the positive holes in the channel region 102, and the positive holes held in the channel region 102 are discharged from one or both of the first impurity layer 101a and the second impurity layer 101b to perform a memory erase operation.
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公开(公告)号：US20220367681A1
公开(公告)日：2022-11-17
申请号：US17742978
申请日：2022-05-12
发明人： Nozomu HARADA , Koji SAKUI
IPC分类号： H01L29/66 , H01L21/8238 , H01L27/12 , H01L29/78 , H01L29/786
摘要： An N+ layer, a Si base material formed of a first channel region and a second channel region, and an N+ layer are disposed parallel to a substrate so as to be connected to each other. A first gate insulating layer that surrounds the first channel region and a second gate insulating layer that surrounds the second channel region are disposed. A first gate conductor layer that surrounds the first gate insulating layer and a second gate conductor layer that surrounds the second gate insulating layer are disposed. The first gate conductor layer is connected to a plate line PL, and the second gate conductor layer is connected to a word line WL. The N+ layer is connected to a source line, and the N+ layer is connected to a bit line BL. These constitute one dynamic flash memory cell. A plurality of cells are disposed in the vertical direction and in the horizontal direction relative to the substrate to form a dynamic flash memory.
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公开(公告)号：US20220367680A1
公开(公告)日：2022-11-17
申请号：US17740669
申请日：2022-05-10
发明人： Koji SAKUI , Nozomu HARADA
IPC分类号： H01L29/66 , H01L21/8238 , H01L27/12 , H01L29/78 , H01L29/786
摘要： A memory device includes pages arranged in columns and each constituted by a plurality of memory cells on a substrate, voltages applied to a first gate conductor layer, a second gate conductor layer, a first impurity layer, and a second impurity layer in each memory cell included in each of the pages are controlled to perform a page write operation of retaining, inside a channel semiconductor layer, a group of positive holes generated by an impact ionization phenomenon or by a gate-induced drain leakage current, and the voltages applied to the first gate conductor layer, the second gate conductor layer, the first impurity layer, and the second impurity layer are controlled to perform a page erase operation of discharging the group of positive holes from inside the channel semiconductor layer. The first impurity layer of the memory cell is connected to a source line, the second impurity layer thereof is connected to a bit line, one of the first gate conductor layer or the second gate conductor layer thereof is connected to a word line, the other of the first gate conductor layer or the second gate conductor layer thereof is connected to a first driving control line, and the bit lines are connected to sense amplifier circuits with a switch circuit therebetween. In a page read operation, page data in a group of memory cells selected by the word line is read to the sense amplifier circuits, and in a page addition read operation, at least two sets of page data selected by at least two word lines in multiple selection are added up for each of the bit lines and read to a corresponding one of the sense amplifier circuits.
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公开(公告)号：US20220367470A1
公开(公告)日：2022-11-17
申请号：US17741956
申请日：2022-05-11
发明人： Nozomu HARADA , Koji SAKUI
IPC分类号： H01L27/108 , G11C11/404 , G11C11/4096
摘要： There are provided the steps of forming an N+ layer 21a and a Si pillar 26 on a substrate 20, the N+ layer 21a being connected to a source line SL, the Si pillar 26 standing in a vertical direction and being composed of a P+ layer 22a in a center portion thereof and a P layer 25a surrounding the P+ layer 22a; forming an N+ layer 3b and HfO2 layers 28a and 28b of gate insulating layers on the P+ layer 22a, the N+ layer 3b being connected to a bit line BL, the HfO2 layers 28a and 28b surrounding the Si pillar 26; and forming a TiN layer 30a of a gate conductor layer and a TiN layer 30b of a gate conductor layer, the TiN layer 30a surrounding the HfO2 layer 28a and being connected to a plate line PL, the TiN layer 30b surrounding the HfO2 layer 28b and being connected to a word line WL. Voltages to be applied to the source line SL, the plate line PL, the word line WL, and the bit line BL are controlled to perform a data write operation for holding a hole group generated by an impact ionization phenomenon or a gate induced drain leakage current in the Si pillar 26 and a data erase operation for discharging the hole group from within the Si pillar 26.
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公开(公告)号：US20220367469A1
公开(公告)日：2022-11-17
申请号：US17741914
申请日：2022-05-11
发明人： Koji SAKUI , Nozomu HARADA
IPC分类号： H01L27/108 , G11C11/404 , G11C11/4096
摘要： A memory device includes pages, each being composed of a plurality of memory cells arrayed on a substrate in row form. The memory device controls voltages to be applied to a first gate conductor layer, a second gate conductor layer, a first impurity region, and a second impurity region of each of the memory cells included in the pages to perform a page write operation of holding a hole group formed by an impact ionization phenomenon or a gate induced drain leakage current in a channel semiconductor layer, and controls voltages to be applied to the first gate conductor layer, the second gate conductor layer, the third gate conductor layer, the fourth gate conductor layer, the first impurity region, and the second impurity region to perform a page erase operation of removing the hole group out of the channel semiconductor layer. The first impurity layer of each of the memory cells is connected to a source line, the second impurity region is connected to a bit line, one of the first gate conductor layer and the second gate conductor layer is connected to a word line, and the other is connected to a first driving control line. The bit line is connected to a sense amplifier circuit via a switching circuit. When in a page read operation, the memory device reads page data in a memory cell group selected by the word line to the bit line, and performs charge sharing between the bit line and a charge sharing node of the switching circuit opposite to the bit line to accelerate a read determination by the sense amplifier circuit.
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公开(公告)号：US20220366986A1
公开(公告)日：2022-11-17
申请号：US17741975
申请日：2022-05-11
发明人： Koji SAKUI , Nozomu HARADA
摘要： A memory device includes pages, each being composed of a plurality of memory cells arrayed on a substrate in row form, and controls voltages to be applied to a first gate conductor layer, a second gate conductor layer, a first impurity layer, and a second impurity layer of each of the memory cells included in the pages to perform a page write operation of holding a hole group generated by an impact ionization phenomenon or a gate induced drain leakage current in a channel semiconductor layer, and controls voltages to be applied to the first gate conductor layer, the second gate conductor layer, the third gate conductor layer, the fourth gate conductor layer, the first impurity layer, and the second impurity layer to perform a page erase operation of removing the hole group out of the channel semiconductor layer. The first impurity layer of the each of the memory cells is connected to a source line, the second impurity layer is connected to a bit line, one of the first gate conductor layer and the second gate conductor layer is connected to one of word lines, and the other is connected to a first driving control line. The first driving control line is provided in common for adjacent ones of the pages, and when in the page erase operation, the memory device applies pulsed voltages to one of the word lines which performs the page erase operation and the first driving control line, and applies a fixed voltage to another one of the word lines which is not selected to perform the page erase operation.
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公开(公告)号：US20220320097A1
公开(公告)日：2022-10-06
申请号：US17706880
申请日：2022-03-29
发明人： Nozomu HARADA , Koji SAKUI
IPC分类号： H01L27/108
摘要： In a dynamic flash memory cell including a HfO2 layer and a TiN layer surrounding a lower portion of a Si pillar standing on a P-layer substrate, a HfO2 layer and a TiN layer surrounding an upper portion of the Si pillar, and N+ layers connecting to a bottom portion and a top portion of the Si pillar, and a Fin transistor including a SiO2 layer surrounding a lower portion of a Si pillar standing also on the P-layer substrate, a HfO2 layer and a TiN layer surrounding an upper portion of the Si pillar, and N+ layers connecting to both side surfaces of the upper portion of the Si pillar, the bottom portion positions of the Si pillar and the Si pillar are both at Position A, and the bottom portions of an SGT transistor unit constituted by, in the upper portion of the Si pillar, the HfO2 layer and the TiN layer and a Fin transistor unit constituted by, in the upper portion of the Si pillar, the HfO2 layer and the TiN layer are both at Position B.
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公开(公告)号：US20220254790A1
公开(公告)日：2022-08-11
申请号：US17730561
申请日：2022-04-27
发明人： Fujio MASUOKA , Nozomu HARADA
IPC分类号： H01L27/11 , H01L27/105
摘要： A bottom portion of a Ta pillar serving as a contact portion is connected to an N+ layer and a P+ layer, and a gate HfO2 layer is connected to side surfaces of Si pillars and a Ta pillar serving as a contact portion and an upper surface of a SiO2 layer between the Si pillars and the Ta pillar serving as the contact portion. Gate TiN layers are provided on a side surface of the gate HfO2 layer surrounding the Si pillars. Midpoints of the Si pillars and the Ta pillar serving as the contact portion are on one first line in plan view.
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