公开(公告)号：US20170220706A1

公开(公告)日：2017-08-03

申请号：US13822625

申请日：2010-09-13

申请人： Jacob J. ORBON ,  Eric VOLKERINK

发明人： Jacob J. ORBON ,  Eric VOLKERINK

IPC分类号： G06F17/50

CPC分类号： G06F17/504 ,  G06F2217/10

摘要： A method for statistically analyzing structural test information to identify at least one yield loss mechanism includes executing a plurality of instructions on a computer system. The executed instructions cause the computer system to perform the steps of: 1) identifying potential root causes for items of structural test information obtained for a plurality of semiconductor devices; 2) statistically analyzing the items of structural test information to identify at least one non-random device failure signature within the items of structural test information; and 3) identifying from the potential root causes a probable root cause for at least a first of the at least one non-random device failure signature.

公开(公告)号：US08068537B2

公开(公告)日：2011-11-29

申请号：US11919388

申请日：2006-03-02

申请人： Bernhard Roth

发明人： Bernhard Roth

IPC分类号： H04L5/14

CPC分类号： H04L5/1423

摘要： A communication circuit for providing a bi-directional data transmission over a signal line, thereby receiving a first digital data stream and transmitting a corresponding first signal into a near end of a signal line to a remote device, the remote device being connected to a far end of the signal line, receiving a second signal at the near end of the signal line from the remote device and deriving a second digital data stream therefrom, having a replica generator for providing, in response to the first digital data stream or a signal derived therefrom, a replica signal, and an extraction circuit for extracting the second digital data stream from the second signal in response to the replica signal and a comparator signal deduced from the near end of the signal line and an automatic test equipment having a plurality of communication circuits each providing a bi-directional data transmission.

摘要翻译： 一种用于通过信号线提供双向数据传输的通信电路，从而接收第一数字数据流并将对应的第一信号发送到远程设备的信号线的近端，远程设备连接到远端 在信号线的末端接收来自远程设备的信号线近端处的第二信号并从其导出第二数字数据流，具有副本发生器，用于响应于第一数字数据流或导出的信号 复制信号和提取电路，用于响应于复制信号从第二信号中提取第二数字数据流，以及从信号线的近端推断的比较器信号，以及具有多个通信的自动测试设备 每个电路提供双向数据传输。

公开(公告)号：US20110238345A1

公开(公告)日：2011-09-29

申请号：US12671892

申请日：2008-02-20

申请人： Pierre Gauthier ,  Maximilian Weinzierl ,  David Spiteri ,  Bela Szendrenyi

发明人： Pierre Gauthier ,  Maximilian Weinzierl ,  David Spiteri ,  Bela Szendrenyi

IPC分类号： G01R19/00 ,  G01R19/10

CPC分类号： G01R31/002

摘要： A system (100) for detecting an electrostatic discharge event with respect to a device (110) to be monitored comprises a current measurement device (140) configured to measure a current flowing via a power supply connection (120) connecting the device to be monitored with the power supply to obtain a current measurement signal representing the current or a current component. Alternatively, a current flowing through a protective earth connection (180) connecting the device to be monitored with the protective earth is measured to obtain the measurement signal. The system comprises an electrostatic discharge event detector configured to detect an electrostatic discharge event in response to a pulse of the current measurement signal. The system may optionally comprise data processing of current measurement signals or values.

摘要翻译： 一种用于检测相对于待监测的装置（110）的静电放电事件的系统（100），包括：电流测量装置（140），被配置为测量经由连接待监测装置的电源连接（120）流动的电流 利用电源来获得表示当前或当前分量的电流测量信号。 或者，测量流过通过保护接地连接（180）连接被监视设备与保护接地的电流，以获得测量信号。 该系统包括静电放电事件检测器，其配置为响应于当前测量信号的脉冲来检测静电放电事件。 系统可以可选地包括当前测量信号或值的数据处理。

公开(公告)号：US08005633B2

公开(公告)日：2011-08-23

申请号：US11347888

申请日：2006-02-06

申请人： Lee Alton Barford ,  Nicholas Tufillaro ,  Ajay Khoche

发明人： Lee Alton Barford ,  Nicholas Tufillaro ,  Ajay Khoche

IPC分类号： G01R23/16

CPC分类号： G01R31/2841

摘要： An excitation signal generator (“ESG”) is described. The ESG generates an minimized excitation signal for use in a test system to generate a functional model of a device under test (“DUT”) where extreme values of the minimized excitation signal are increased toward a central value without changing the power spectrum at the DUT.

摘要翻译： 描述了激励信号发生器（“ESG”）。 ESG生成最小化的激励信号，用于测试系统，以产生被测器件（“DUT”）的功能模型，其中最小化激励信号的极限值朝向中心值增加，而不改变DUT处的功率谱 。

公开(公告)号：US20110140737A1

公开(公告)日：2011-06-16

申请号：US13000348

申请日：2008-06-20

申请人： Jochen Rivoir

发明人： Jochen Rivoir

IPC分类号： H03D13/00

CPC分类号： G04F10/005

摘要： An apparatus for estimating data relating to a time difference between two events includes a delay line having a plurality of stages. Each stage has a delay difference between a first delay in a first part and a second delay in a second part. This delay difference is measured by a phase arbiter in each stage, which outputs an indication signal indicating whether the first event of two events in the first part precedes or succeeds a second event of the two events in the second part. A summation device is provided for summing over the indication signals of the plurality of stages to obtain a sum value. The sum value indicates a time difference estimate.

摘要翻译： 用于估计与两个事件之间的时间差有关的数据的装置包括具有多个级的延迟线。 每个级在第一部分的第一延迟和第二部分的第二延迟之间具有延迟差。 该延迟差由每个阶段中的相位仲裁器来测量，其输出指示第一部分中的两个事件的第一事件是否在第二部分中的两个事件的第二事件之前或成功的指示信号。 提供一个求和装置，用于对多个级的指示信号求和以获得和值。 和值表示时差估计。

公开(公告)号：US07928755B2

公开(公告)日：2011-04-19

申请号：US12276290

申请日：2008-11-21

申请人： Edmundo de la Puente ,  David D. Eskeldson

发明人： Edmundo de la Puente ,  David D. Eskeldson

IPC分类号： G01R31/26

CPC分类号： G01R31/3172 ,  G01R31/31712

摘要： In one embodiment, apparatus for testing at least one device under test (DUT) includes a tester input/output (I/O) node, a DUT I/O node, a remote pin electronics block, a bypass circuit, and a control system. The remote pin electronics block provides a test function and is coupled between the tester I/O node and the DUT I/O node. The bypass circuit is coupled between the tester I/O node and the DUT I/O node and provides a signal bypass path between the tester I/O node and the DUT I/O node. The signal bypass path bypasses the test function provided by the remote pin electronics block. The control system is configured to enable and disable the bypass circuit. Methods for using this and other related apparatus to test one or more DUTs are also disclosed.

摘要翻译： 在一个实施例中，用于测试至少一个待测器件（DUT）的装置包括测试器输入/输出（I / O）节点，DUT I / O节点，远程引脚电子模块，旁路电路和控制系统 。 远程引脚电子模块提供测试功能，并连接在测试仪I / O节点和DUT I / O节点之间。 旁路电路耦合在测试仪I / O节点和DUT I / O节点之间，并在测试仪I / O节点和DUT I / O节点之间提供信号旁路。 信号旁路通路旁路由远程引脚电子模块提供的测试功能。 控制系统配置为启用和禁用旁路电路。 还公开了使用这种和其它相关设备来测试一个或多个DUT的方法。

公开(公告)号：US07865788B2

公开(公告)日：2011-01-04

申请号：US11941026

申请日：2007-11-15

申请人： Phillip D. Burlison ,  Mei-Mei Su ,  John K. Frediani

发明人： Phillip D. Burlison ,  Mei-Mei Su ,  John K. Frediani

IPC分类号： G11C29/00

CPC分类号： G01R31/318544

摘要： A failure mask memory is added to a semiconductor tester. In conjunction with a new failure filter, failures may be ignored or used to update the contents of failure mask memory. Only the first instance of a failure is reported reducing the size of test data logs.

摘要翻译： 将故障掩模存储器添加到半导体测试器。 结合新的故障过滤器，故障可能被忽略或用于更新故障掩码存储器的内容。 报告只有第一个失败的实例减少测试数据日志的大小。

公开(公告)号：US07853846B2

公开(公告)日：2010-12-14

申请号：US11931847

申请日：2007-10-31

申请人： Stephen A. Cannon ,  Richard C. Dokken ,  Alfred L. Crouch ,  Gary A. Winblad

发明人： Stephen A. Cannon ,  Richard C. Dokken ,  Alfred L. Crouch ,  Gary A. Winblad

IPC分类号： G01R31/28

CPC分类号： G01R31/318544 ,  G01R31/318525 ,  G01R35/00

摘要： A method for determining that failures in semiconductor test are due to a defect potentially causing a hold time violation in a scan cell in a scan chain, counting the number of potential defects, and, if possible, localizing, and ameliorating hold time defects in a scan chain.

摘要翻译： 用于确定半导体测试中的故障的方法是由于潜在地导致扫描链中的扫描单元中的保持时间违规的缺陷，计数潜在缺陷的数量，以及如果可能的话，定位和改善保持时间缺陷 扫描链。

公开(公告)号：US07853828B2

公开(公告)日：2010-12-14

申请号：US11432176

申请日：2006-05-11

申请人： Jeffrey Johnson ,  Ben Rogel-Favila ,  Alan Davis

发明人： Jeffrey Johnson ,  Ben Rogel-Favila ,  Alan Davis

IPC分类号： G06F11/00

CPC分类号： G06F11/273

摘要： A hardware independent and graphically extensible tester state browsing technique for observing and modifying operating state of test equipment includes accessing a descriptor file describing an architecture of the test equipment, invoking a set of plugins associated with one or more subsystems of the test equipment, and displaying a map with a set of drill-down mechanisms each associated with different ones of the subsystems of the test equipment which invoke the respective plugin associated with its corresponding respective subsystem.

摘要翻译： 用于观察和修改测试设备的操作状态的硬件无关和图形可扩展的测试器状态浏览技术包括访问描述测试设备的架构的描述符文件，调用与测试设备的一个或多个子系统相关联的一组插件，以及显示 具有一组下拉机制的地图，每个相关联的测试设备的子系统的不同子系统调用与其对应的相应子系统相关联的相应插件。

公开(公告)号：US07847716B2

公开(公告)日：2010-12-07

申请号：US12376121

申请日：2006-08-01

申请人： Jochen Rivoir

发明人： Jochen Rivoir

IPC分类号： H03M3/00

CPC分类号： H03M7/3024

摘要： An asynchronous sigma delta digital to analog converter for converting a digital input signal into an analog output signal, the digital to analog converter having an asynchronous sigma delta modulator having a low pass filter and a comparator and being supplied with the digital input signal, and a clock sample unit adapted to sample a signal processed by the comparator based on a clock signal, thereby generating the analog output signal.

摘要翻译： 一种用于将数字输入信号转换为模拟输出信号的异步Σ-Δ数模转换器，所述数模转换器具有具有低通滤波器和比较器的异步Σ-Δ调制器，并且被提供有数字输入信号，以及 时钟采样单元，其适于基于时钟信号对由比较器处理的信号进行采样，从而产生模拟输出信号。