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    Modular test environment for a plurality of test objects
    1.
    发明授权
    Modular test environment for a plurality of test objects 有权

    公开(公告)号：US09989593B2

    公开(公告)日：2018-06-05

    申请号：US14783419

    申请日：2014-04-04

    申请人： Airbus Defence and Space GmbH

    发明人： Philipp Wager ,  Bernd Schumacher

    IPC分类号： G01R31/319 ,  G01R31/28 ,  G06F11/36

    CPC分类号： G01R31/319 ,  G01R31/2834 ,  G01R31/31907 ,  G06F11/3664

    摘要： The present invention relates to an arrangement for providing a testing environment for the testing of test objects. The testing environment includes a first test object receiving apparatus and a second test object receiving apparatus, each of which are configured to receive a test object. The testing environment also includes a connection interface configured to connect the first test object receiving apparatus and the second test object receiving apparatus to the testing environment. In one embodiment, the first test object receiving apparatus has a first external connection interface, and the second test object receiving apparatus has a second external connection interface, wherein said first and second external connection interfaces are configured to be selectively coupled with the connection interface of the testing environment.

    API-based pattern-controlled test on an ATE
    2.
    发明授权
    API-based pattern-controlled test on an ATE 有权

    公开(公告)号：US09989591B2

    公开(公告)日：2018-06-05

    申请号：US14687259

    申请日：2015-04-15

    申请人： Advantest Corporation

    发明人： Liang Ge ,  Jia-Min Wang

    IPC分类号： G06F11/22 ,  G06F17/50 ,  G01R31/3177 ,  G01R31/319 ,  G01R31/28 ,  G06F11/273

    CPC分类号： G01R31/3177 ,  G01R31/2834 ,  G01R31/31907 ,  G01R31/31908 ,  G06F11/263 ,  G06F11/2736

    摘要： Method and apparatus for performing Pattern-Controlled tests on an automatic test equipment (ATE). The ATE includes a diagnostic instrument and a control device. An application programming interface (API) is installed in the control device and operates to interact with a test program and thereby automatically controls the diagnostic instrument to perform a test. The test program is coded in a high-level programming language and defines a plurality of operation events for the test based on user input. The API identifies the operational events and determines respective operational types associated therewith. Events of an operational type are assigned to a respective pattern label. The pattern labels are then aggregated into a pattern burst which is downloaded to the diagnostic instrument.

    METHOD FOR OPERATING A TEST APPARATUS AND A TEST APPARATUS
    3.
    发明申请
    METHOD FOR OPERATING A TEST APPARATUS AND A TEST APPARATUS 审中-公开

    公开(公告)号：US20180017620A1

    公开(公告)日：2018-01-18

    申请号：US15716516

    申请日：2017-09-27

    申请人： Advantest Corporation

    发明人： Wolfgang Horn

    IPC分类号： G01R31/319

    CPC分类号： G01R31/31907

    摘要： A method for operating a test apparatus including a plurality of shared resources is shown, wherein the plurality of shared resources can be used in different instruments. The method includes blocking a first set of resource blockers when a first instrument, which requires a first subset of the shared resources, is to be executed. Furthermore, the method tries to block a second set of resource blockers, when a second instrument, which requires a second subset of the shared resources, is to be executed. Therefore, the first set of resource blockers is different from the second set of resource blockers and a plurality of resource blockers are assigned to a shared resource, which is involved in a conflicting combination of instruments and in a non-conflicting combination of instruments.

    Data management with spectrum analyzers
    5.
    发明授权
    Data management with spectrum analyzers 有权

    公开(公告)号：US09618549B2

    公开(公告)日：2017-04-11

    申请号：US14677167

    申请日：2015-04-02

    申请人： Research Electronics International

    发明人： Bruce R. Barsumian ,  Thomas H. Jones

    IPC分类号： H04B17/00 ,  G01R23/16 ,  G01R31/319 ,  G01R31/302

    CPC分类号： G01R23/16 ,  G01R13/02 ,  G01R31/3025 ,  G01R31/31907

    摘要： A spectrum analyzer contains a number of improvements that adapt it to common commercial uses. The spectrum analyzer is capable of automatically wirelessly receiving and synchronizing frequency spectrum data collected from multiple remote spectrum analyzers with respect to frequency, time and location. A selector function is used to create composite frequency data sets from multiple frequency data sets while allowing retroactive identification and examination of the original frequency data. An improved non-linear graphical display of the frequency spectrum data is created by automatically expanding the resolution of frequency axis for frequency ranges having signals of interest and contracting the resolution of the frequency axis of frequency ranges having no signals of interest.

    BACKPLANE TESTING SYSTEM
    6.
    发明申请
    BACKPLANE TESTING SYSTEM 审中-公开
    背板测试系统

    公开(公告)号：US20170059656A1

    公开(公告)日：2017-03-02

    申请号：US15350902

    申请日：2016-11-14

    申请人： Dell Products L.P.

    发明人： Umesh Chandra ,  Timothy Thinh Mai

    IPC分类号： G01R31/317 ,  G01R31/3177

    CPC分类号： G01R31/31703 ,  G01R31/31708 ,  G01R31/31712 ,  G01R31/31716 ,  G01R31/3177 ,  G01R31/31813 ,  G01R31/31907 ,  G06F11/2221

    摘要： A backplane testing system includes a test backplane coupled to a test device chassis and including a first connector system, a second connector system, and channels that connect the first connector system and the second connector system. A first test device in a first test device slot on the test device chassis engages the first connector system and provides a loop back circuit for the first connector system. A second test device in a second test device slot on the test device chassis engages the second connector system. The second test device sends a test signal through a channel on the test backplane such that the test signal is provided to the loop back circuit on the first test device and received back through the channel. The second test device analyzes the test signal that is received to determine a testing compliance of the channel on the test backplane.

    摘要翻译： 背板测试系统包括耦合到测试设备机箱并包括第一连接器系统，第二连接器系统和连接第一连接器系统和第二连接器系统的通道的测试背板。 测试设备底盘上的第一测试设备插槽中的第一测试设备接合第一连接器系统，并为第一连接器系统提供环回电路。 第二测试设备在测试设备底盘上的第二测试设备插槽中接合第二连接器系统。 第二测试设备通过测试背板上的通道发送测试信号，使得测试信号被提供给第一测试设备上的环回电路并通过通道接收回来。 第二个测试设备分析接收到的测试信号，以确定测试背板上的通道的测试符合性。

    Test system
    7.
    发明授权
    Test system 有权
    测试系统

    公开(公告)号：US09484116B1

    公开(公告)日：2016-11-01

    申请号：US14827743

    申请日：2015-08-17

    申请人： ADVANTEST CORPORATION

    发明人： Masaaki Kosugi ,  Takashi Ohguro ,  Michisuke Sakamoto ,  Toshiro Fujii ,  Takahiro Honma ,  Hideto Omori

    IPC分类号： G01R31/28 ,  G06F11/00 ,  G11C29/38 ,  G11C29/36 ,  G01R31/319

    CPC分类号： G11C29/38 ,  G01R31/28 ,  G01R31/31903 ,  G01R31/31907 ,  G01R31/31935 ,  G11C29/56 ,  G11C29/56008 ,  G11C29/70

    摘要： At least one general-purpose server is connected to a PE module via Ethernet (trademark). A control unit of the PE module controls a PE circuit and multiple fail memory in a real-time manner, temporarily stores fail information stored in the multiple fail memory, performs data processing on the fail information, and transfers the fail information thus processed to the general-purpose server. Each general-purpose server is controlled according to a computer program so as to perform redundancy analysis for a DUT based on the data received from the PE module.

    摘要翻译： 至少一个通用服务器通过以太网（商标）连接到PE模块。 PE模块的控制单元实时控制PE电路和多个故障存储器，临时存储存储在多个故障存储器中的故障信息，对故障信息执行数据处理，并将所处理的故障信息传送到 通用服务器。 根据计算机程序控制每个通用服务器，以便根据从PE模块接收到的数据对DUT进行冗余分析。

    SEMICONDUCTOR DEVICE TESTER WITH DUT DATA STREAMING
    8.
    发明申请
    SEMICONDUCTOR DEVICE TESTER WITH DUT DATA STREAMING 审中-公开
    具有DUT数据流的半导体器件测试仪

    公开(公告)号：US20160313370A1

    公开(公告)日：2016-10-27

    申请号：US14655684

    申请日：2014-07-28

    申请人： INTEL CORPORATION

    发明人： James Neeb ,  Vineet Pancholi ,  Gerard McSweeney ,  Shelby Rollins ,  Chris Johnson ,  Nathan Blackwell ,  Bradly L. Inman ,  Steven Lill ,  Rodney J. Christner ,  Phillip Barnes

    IPC分类号： G01R1/02 ,  G01R31/28 ,  G01R29/26

    CPC分类号： G01R1/025 ,  G01R29/26 ,  G01R31/2896 ,  G01R31/31907

    摘要： A method is described that includes configuring multiple test units of a semiconductor device tester with respective information indicating respective storage space within either or both of an off load processing unit and central control unit of the tester. The method further includes streaming DUT data from the test units to their respective storage space within at least one of the off load processing unit and the central control unit such that the test units continually initiate the sending of their respective DUT data to their respective storage space.

    摘要翻译： 描述了一种方法，其包括配置半导体器件测试器的多个测试单元，其各自的信息指示测试仪的卸载处理单元和中央控制单元中的任一个或两者中的相应存储空间。 该方法还包括将DUT数据从测试单元传送到其关闭负载处理单元和中央控制单元中的至少一个中的相应存储空间，使得测试单元连续地开始将它们各自的DUT数据发送到它们各自的存储空间 。

    Test IP-Based A.T.E. Instrument Architecture
    10.
    发明申请
    Test IP-Based A.T.E. Instrument Architecture 审中-公开

    公开(公告)号：US20160238657A1

    公开(公告)日：2016-08-18

    申请号：US15008594

    申请日：2016-01-28

    申请人： Allen Czamara ,  Ed Paulsen ,  Lev Alperovich

    发明人： Allen Czamara ,  Ed Paulsen ,  Lev Alperovich

    IPC分类号： G01R31/317 ,  G01R31/3177 ,  G01R31/28

    CPC分类号： G01R31/2834 ,  G01R31/31704 ,  G01R31/31705 ,  G01R31/31907 ,  G01R31/31908

    摘要： A test system based on multiple instances of reconfigurable instrument IP specifically matched to the device under test may be used in integrating automated testing of semiconductor devices between pre-silicon simulation, post-silicon validation, and production test phases, in one embodiment of software and hardware across all three phases, for different devices. The reconfigurable test system comprises: a tester instrument, instances of instrument IP instantiated in the tester instruments, a computer system, and a test program. The tester instrument connects to a device under test (DUT), and includes FPGAs reconfigurable for the three testing phases. The computer system has a user interface, and a controller connected to the reconfigurable tester instrument via a data bus. The test program stored on the controller, and the controller, instantiates interfaces and protocols, and certain process transactions to support the protocols, into FPGAs, to match device interfaces for each DUT, to execute test sequences.