利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

11 条记录 (耗时 0.014 秒)

    Analog voltage metering system with programmable bit-serial digital signal processors
    1.
    发明授权
    Analog voltage metering system with programmable bit-serial digital signal processors 失效
    具有可编程位串行数字信号处理器的模拟电压计量系统

    公开(公告)号：US5448747A

    公开(公告)日：1995-09-05

    申请号：US250122

    申请日：1994-05-27

    申请人： Steven L. Garverick ,  Kenji Fujino

    发明人： Steven L. Garverick ,  Kenji Fujino

    IPC分类号： G01R19/00 ,  G01R21/00 ,  G01R21/133 ,  G05B19/042 ,  G06F7/544 ,  G06F15/78 ,  G06F17/10 ,  G06F7/38

    CPC分类号： G06F15/7842 ,  G05B19/0423 ,  G06F7/5443 ,  G06F7/5446 ,  G01R21/006 ,  G05B2219/25254

    摘要： A monolithic integrated circuit as may be used in combination with a plurality of sensors for generating respective sensor output signals, which monolithic integrated circuit includes means for converting each sensor output signal to bit-serial digital format, together with some initial processing circuitry comprising a bit-serial multiply-add processor. This processor includes a bit-serial digital multiplier for multiplying a first digital processor input signal in bit-serial form by a second digital processor input signal to generate a digital product signal, a digital adder for adding a third digital processor input signal to the digital product signal to generate a digital sum signal, and means for supplying a digital processor output signal with bits correspond-ing to those of said digital sum signal. A memory system provides memory for storing program instructions, memory for storing successive values of the second digital processor input signal, memory for storing successive values of the third digital processor input signal, and memory for storing successive values of the digital processor output signal as written into the memory system. The first digital processor input signal can be selected from among the sensor output signals as converted to bit-serial digital format. The second digital processor input signals applied to the bit-serial multiply-add processor are at least at selected times read from the memory system, as are the third digital processor input signals applied to the bit-serial multiply-add processor. A controller retrieves stored program instructions in a prescribed order from the memory for storing program instructions and generates control signals for controlling at least the reading and writing of the memory system, as well as the selecting of the first digital processor input signal.

    摘要翻译： 可以与用于产生各个传感器输出信号的多个传感器组合使用的单片集成电路，该单片集成电路包括用于将每个传感器输出信号转换为位串行数字格式的装置，以及一些初始处理电路，包括一位 - 系列乘法加法处理器。 该处理器包括位串行数字乘法器，用于将位串行形式的第一数字处理器输入信号乘以第二数字处理器输入信号以产生数字乘积信号;数字加法器，用于将第三数字处理器输入信号加到数字 产生信号以产生数字和信号，以及用于向数字处理器输出信号提供与所述数字和信号相对应的位的装置。 存储器系统提供用于存储程序指令的存储器，用于存储第二数字处理器输入信号的连续值的存储器，用于存储第三数字处理器输入信号的连续值的存储器和用于存储数字处理器输出信号的连续值的存储器， 进入内存系统。 可以从传感器输出信号中选择第一个数字处理器输入信号，转换为位串行数字格式。 应用于位串行乘法加法处理器的第二数字处理器输入信号至少在从存储器系统读取的选定时间，以及施加到位串行乘法加法处理器的第三数字处理器输入信号。 控制器从用于存储程序指令的存储器中以规定的顺序检索存储的程序指令，并且生成用于至少控制存储器系统的读取和写入以及第一数字处理器输入信号的选择的控制信号。

    Digital signal processor for selectively performing cordic, division or square-rooting procedures
    5.
    发明授权
    Digital signal processor for selectively performing cordic, division or square-rooting procedures 失效
    数字信号处理器，用于选择性地执行线性，分割或正方形生成程序

    公开(公告)号：US5134578A

    公开(公告)日：1992-07-28

    申请号：US685340

    申请日：1991-04-15

    申请人： Steven L. Garverick ,  Kenji Fujino

    发明人： Steven L. Garverick ,  Kenji Fujino

    IPC分类号： G01R19/00 ,  G01R21/00 ,  G01R21/133 ,  G05B19/042 ,  G06F7/544 ,  G06F15/78 ,  G06F17/10

    CPC分类号： G06F15/7842 ,  G05B19/0423 ,  G06F7/5443 ,  G06F7/5446 ,  G01R21/006 ,  G05B2219/25254

    摘要： A bit-serial processor for selectively carrying out the sequential steps of performing by successive approximations Coordinate Rotation Digital Computation (CORDIC), non-restoring division or non-restoring square rooting calculations is suitable for inclusion in a monolithic integrated circuit with a plurality of sensors for generating respective sensor output signals, circuitry for converting each sensor output signal to bit-serial digital format, and a bit-serial muliptly-add processor. Together with an electrically-erasable programmable read-only memory and a plurality of current transformers, the monolithic integrated circuit implements a system for metering a-c power main conductors.

    摘要翻译： 用于选择性地执行通过逐次逼近执行的顺序步骤的位串行处理器坐标旋转数字计算（CORDIC），非恢复分割或非恢复平方根生根计算适用于包含在具有多个传感器的单片集成电路 用于产生相应的传感器输出信号，用于将每个传感器输出信号转换为比特串行数字格式的电路和一个位串行多媒体加法处理器。 与电可擦除可编程只读存储器和多个电流互感器一起，单片集成电路实现用于计量a-c电源主导体的系统。

    Integrated skid with multiple-motor controller
    6.
    发明授权
    Integrated skid with multiple-motor controller 失效
    集成滑道与多电机控制器

    公开(公告)号：US07733037B2

    公开(公告)日：2010-06-08

    申请号：US10816092

    申请日：2004-04-01

    申请人： Kenneth Marks ,  Douglas A. Parsons

    发明人： Kenneth Marks ,  Douglas A. Parsons

    IPC分类号： H02P5/46

    CPC分类号： G05B19/042 ,  G05B2219/25254

    摘要： An integrated skid system integrates the functions of multiple skids into a single skid to reduce the skid footprint and the complexity of the overall system. A multi-motor controller monitors the devices on the integrated skid to maintain proper temperature, pressure and current draw in the devices. Base on this information, the multi-motor controller can make decisions on faults and fault accommodation and communicate with a main controller regarding the operating states of the skid devices via a single serial or Ethernet-type connection.

    摘要翻译： 综合的滑行系统将多个滑行的功能集成到一个单一滑道中，以减少滑行足迹和整个系统的复杂性。 多电机控制器监控集成滑轨上的设备，以便在设备中保持适当的温度，压力和电流消耗。 基于该信息，多电动机控制器可以通过单个串行或以太网类型的连接来做出关于故障和故障调节的决定并与主控制器通信关于滑动装置的操作状态。

    Integrated skid with multiple-motor controller
    7.
    发明申请
    Integrated skid with multiple-motor controller 失效
    集成滑道与多电机控制器

    公开(公告)号：US20050218841A1

    公开(公告)日：2005-10-06

    申请号：US10816092

    申请日：2004-04-01

    申请人： Kenneth Marks ,  Douglas Parsons

    发明人： Kenneth Marks ,  Douglas Parsons

    IPC分类号： F04C15/00 ,  G05B19/042 ,  H02P5/46

    CPC分类号： G05B19/042 ,  G05B2219/25254

    摘要： An integrated skid system integrates the functions of multiple skids into a single skid to reduce the skid footprint and the complexity of the overall system. A multi-motor controller monitors the devices on the integrated skid to maintain proper temperature, pressure and current draw in the devices. Base on this information, the multi-motor controller can make decisions on faults and fault accommodation and communicate with a main controller regarding the operating states of the skid devices via a single serial or Ethernet-type connection.

    摘要翻译： 综合的滑行系统将多个滑行的功能集成到一个单一滑道中，以减少滑行足迹和整个系统的复杂性。 多电机控制器监控集成滑轨上的设备，以便在设备中保持适当的温度，压力和电流消耗。 基于该信息，多电动机控制器可以通过单个串行或以太网类型的连接来做出关于故障和故障调节的决定并与主控制器通信关于滑动装置的操作状态。

    Processor interfacing to memory-centric computing engine
    8.
    发明授权
    Processor interfacing to memory-centric computing engine 失效
    处理器连接到以内存为中心的计算引擎

    公开(公告)号：US06691206B1

    公开(公告)日：2004-02-10

    申请号：US08869148

    申请日：1997-06-04

    申请人： Richard Rubinstein

    发明人： Richard Rubinstein

    IPC分类号： G06F1200

    CPC分类号： G11C8/10 ,  G05B19/042 ,  G05B2219/15118 ,  G05B2219/25254 ,  G05B2219/25305 ,  G05B2219/25431 ,  G06F12/0284 ,  H04N19/61 ,  Y02D10/13

    摘要： Methods and apparatus are disclosed for interfacing a processor bus or CPU to a computation engine to carry out selected tasks with improved efficiency in the computation engine. The computation engine is controlled by an MCC memory-centric controller that provides microcoded operation of the engine independently of the CPU. Essential interfacing between the processor bus and the computation engine includes storing microcode in a separate memory accessible to the MCC controller, or downloading microcode from the CPU/processor bus as needed for a specific task. The MCC controller can reconfigure the computation engine, such as memory block allocation, word size, etc. under microcode control, so that new or user-proprietary algorithms such as those used in dsp can be implemented using a standard computation engine without redesign. Execution of selected tasks on the computation engine is triggered automatically by decoding instructions that appear on the processor bus. Such tasks can include dsp, compression, decompression, encryption or other complex computations, and further can include downloading new or updated microcode into the computation engine desired.

    摘要翻译： 公开了用于将处理器总线或CPU连接到计算引擎的方法和装置，以在计算引擎中提高效率来执行所选择的任务。 计算引擎由以MCC为中心的控制器控制，该控制器独立于CPU提供引擎的微编码操作。 处理器总线和计算引擎之间的基本接口包括将微代码存储在MCC控制器可访问的单独存储器中，或者根据特定任务需要从CPU /处理器总线下载微代码。 MCC控制器可以在微代码控制下重新配置计算引擎，如存储块分配，字大小等，从而可以使用标准计算引擎实现新的或用户专有的dsp中使用的算法，而无需重新设计。 通过解码出现在处理器总线上的指令，自动触发在计算引擎上执行选定任务。 这样的任务可以包括dsp，压缩，解压缩，加密或其它复杂的计算，并且还可以包括将新的或更新的微代码下载到所需的计算引擎中。

    Shared, reconfigurable memory architectures for digital signal processing
    10.
    发明授权
    Shared, reconfigurable memory architectures for digital signal processing 失效
    用于数字信号处理的共享可重构存储器架构

    公开(公告)号：US5933855A

    公开(公告)日：1999-08-03

    申请号：US821326

    申请日：1997-03-21

    申请人： Richard Rubinstein

    发明人： Richard Rubinstein

    IPC分类号： G05B19/042 ,  G06F12/02 ,  G11C8/10 ,  H04N7/50 ,  G06F12/00

    CPC分类号： G11C8/10 ,  G05B19/042 ,  G06F12/0284 ,  H04N19/61 ,  G05B2219/15118 ,  G05B2219/25254 ,  G05B2219/25305 ,  G05B2219/25431 ,  Y02B60/1225

    摘要： Architectures and circuits are described for various implementations of a memory-centric computing system for DSP and other compute-intensive applications. A shared, reconfigurable memory system is accessible to both a host processor or controller and to one or more execution units such as a DSP execution unit. By swapping memory space between the processor and the execution unit so as to support continuous execution and I/O, improved performance is achieved while cost is reduced. The shared memory system includes multiple reconfigurable memory segments to allow allocation of various amounts of memory to respective execution units or I/O or DMA channels as needed to optimize performance. A "virtual two-port" solution also is described for using single-port memory in the shared configuration with multiple address sources.

    摘要翻译： 针对DSP和其他计算密集型应用程序的以内存为中心的计算系统的各种实现描述了体系结构和电路。 共享的可重新配置的存储器系统可由主处理器或控制器以及一个或多个执行单元（诸如DSP执行单元）访问。 通过交换处理器和执行单元之间的存储空间，以支持连续执行和I / O，在降低成本的同时实现了改进的性能。 共享存储器系统包括多个可重新配置的存储器段，以允许根据需要将各种量的存储器分配到相应的执行单元或I / O或DMA通道以优化性能。 还描述了在具有多个地址源的共享配置中使用单端口存储器的“虚拟双端口”解决方案。