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公开(公告)号：US12019556B2
公开(公告)日：2024-06-25
申请号：US17704889
申请日：2022-03-25
Applicant: Oracle International Corporation
Inventor： Benjamin John Fuller
IPC: G06F12/0891 , G06F1/32 , G06F12/0804 , G06F12/0831 , G06F13/16
CPC classification number: G06F12/0891 , G06F1/32 , G06F12/0804 , G06F12/0833 , G06F13/1668 , G06F2212/60
Abstract: Techniques are described herein for flushing volatile system memory to persistent memory after the loss of alternating current (AC) power. In some embodiments, the techniques include implementing an extended hold-up window long enough to complete a full flush of processor caches and memory controller buffers using energy available in the bulk capacitors of one or more power supplies after a power outage event. The voltage on the bulk capacitors within the one or more power supply units may be monitored, and a notification may be triggered when a programmable threshold voltage is detected on the bulk capacitors. The system may configure the voltage threshold to indicate that a certain minimum amount of energy used to successfully complete a cache flush operation is available. The techniques allow flushing volatile system caches without relying on battery backup units (BBUs), which may be cumbersome to install and maintain.
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2.发明授权
公开(公告)号：US11989155B2
公开(公告)日：2024-05-21
申请号：US17942816
申请日：2022-09-12
Applicant: UNTETHER AI CORPORATION
Inventor： William Martin Snelgrove , Jonathan Scobbie
CPC classification number: G06F15/8015 , G06F9/3001 , G06F9/30047 , G06F9/3887 , G06F1/32 , G06N3/04 , G06N3/08
Abstract: A computing device includes an array of processing elements mutually connected to perform single instruction multiple data (SIMD) operations, memory cells connected to each processing element to store data related to the SIMD operations, and a cache connected to each processing element to cache data related to the SIMD operations. Caches of adjacent processing elements are connected. The same or another computing device includes rows of mutually connected processing elements to share data. The computing device further includes a row arithmetic logic unit (ALU) at each row of processing elements. The row ALU of a respective row is configured to perform an operation with processing elements of the respective row.
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公开(公告)号：US11971760B2
公开(公告)日：2024-04-30
申请号：US17224891
申请日：2021-04-07
Applicant: Apple Inc.
Inventor： Anne M. Mason
IPC: G06F1/20 , G01K3/00 , G01K7/16 , G01L1/22 , G06F1/18 , G06F1/32 , H05K1/03 , H05K1/09 , H05K1/11 , H05K1/18
CPC classification number: G06F1/206 , G01K3/005 , G01K7/16 , G01L1/22 , G06F1/181 , G06F1/32 , H05K1/0353 , H05K1/09 , H05K1/111 , H05K1/185 , H05K2201/0154 , H05K2201/10151
Abstract: An electronic device may include a printed circuit with a surface-mounted component. The component may produce resistive heating within the printed circuit. Resistive thermal devices (RTDs) may be embedded within the printed circuit. An RTD may at least partially overlap the electrical component. The RTD may include contact pads on a flexible substrate and a meandering conductive trace between the contact pads. The trace may have a resistance varying linearly as a function of temperature. A data acquisition system (DAQ) may measure the resistance of the RTD. Control circuitry may identify the temperature of the printed circuit based on the resistance of the RTD measured by the DAQ and may reduce power consumption by the component when the temperature exceeds a threshold. This may serve to prevent overheating in the printed circuit over time, thereby maximizing the operating life of the printed circuit.
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公开(公告)号：US11904364B1
公开(公告)日：2024-02-20
申请号：US18380190
申请日：2023-10-15
Applicant: GUI GLOBAL PRODUCTS, LTD.
Inventor： Walter G. Mayfield , Daniel Martin Valdez
CPC classification number: B08B1/006 , A45C11/00 , B08B1/002 , B08B11/04 , G06F1/32 , H04M1/21 , H04B1/3816 , H04M1/0266
Abstract: A lens and/or a view screen of an electronic device having at least one case can be cleaned by wiping the view screen with a cleaning component wherein the cleaning component is configured to selectively couple to the at least one case or some other substrate using a magnetic attractive force. The cleaning devices may have secondary applications such as securing fly fishing lures, activating or deactivating a device having a magnetic switch, or preventing sunglasses from sinking. They may also be manufactured without a cleaning component for use with the secondary applications.
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公开(公告)号：US20240028094A1
公开(公告)日：2024-01-25
申请号：US18474377
申请日：2023-09-26
Applicant: Intel Corporation
IPC: G06F1/26 , G06F1/3287 , G06F13/42 , G06F1/32 , G06F1/3203 , G06F1/3296 , G06F9/46 , G06F1/3234 , G06F30/00
CPC classification number: G06F1/266 , G06F1/3287 , G06F13/4282 , G06F1/32 , G06F1/3203 , G06F1/3296 , G06F1/26 , G06F9/46 , G06F1/3243 , G06F30/00 , G06F2213/0016 , Y02B70/10 , Y02D10/00
Abstract: In one embodiment, a processor includes: a plurality of cores; a first storage to store parameter information for a voltage regulator to couple to the processor via a voltage regulator interface; and a power controller to control power consumption of the processor. The power controller may determine a performance state for one or more cores of the processor and include a hardware logic to generate a message for the voltage regulator based at least in part on the parameter information, where this message is to cause the voltage regulator to output a voltage to enable the one or more cores to operate at the performance state. Other embodiments are described and claimed.
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公开(公告)号：US11868265B2
公开(公告)日：2024-01-09
申请号：US17704903
申请日：2022-03-25
Applicant: Oracle International Corporation
Inventor： Benjamin John Fuller
IPC: G06F12/0891 , G06F1/32 , G06F12/0804 , G06F12/0831 , G06F13/16 , G06F1/30 , G06F12/0868
CPC classification number: G06F12/0891 , G06F1/32 , G06F12/0804 , G06F12/0833 , G06F13/1668 , G06F2212/60
Abstract: Techniques are described herein processing asynchronous power transition events while maintaining a persistent memory state. In some embodiments, a system may proxy asynchronous reset events through system logic, which generates an interrupt to invoke a special persistent flush interrupt handler that performs a persistent cache flush prior to invoking a hardware power transition. Additionally or alternatively, the system may include a hardware backup mechanism to ensure all resets and power-transitions requested in hardware reliably complete within a bounded window of time independent of whether the persistent cache flush handler succeeds.
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公开(公告)号：US20230393646A1
公开(公告)日：2023-12-07
申请号：US18237337
申请日：2023-08-23
Applicant: Avinash ANANTHAKRISHNAN , Jeremy SHRALL
Inventor： Avinash ANANTHAKRISHNAN , Jeremy SHRALL
IPC: G06F1/3296 , G06F9/30 , G06F1/28 , G06F1/324 , G06F1/3234 , G06F1/3206 , G06F1/32 , G06F1/3203 , G06F1/3212
CPC classification number: G06F1/3296 , G06F9/30101 , G06F1/28 , G06F1/324 , G06F1/3234 , G06F1/3206 , G06F1/32 , G06F1/3203 , G06F1/3212 , G06F9/30
Abstract: An apparatus is provided, where the apparatus includes a plurality of components, wherein an individual component has a corresponding throttling priority of a plurality of throttling priorities. The apparatus further includes logic to selectively throttle one or more of the plurality of components. In an example, an order in which the one or more of the plurality of components are to be throttled may be based on the plurality of throttling priorities.
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公开(公告)号：US11809549B2
公开(公告)日：2023-11-07
申请号：US16728843
申请日：2019-12-27
Applicant: Intel Corporation
Inventor： Alexander Gendler , Sagi Meller , Gavri Berger , Igor Yanover
CPC classification number: G06F21/54 , G06F1/32 , G06F9/3802 , G06F21/561 , G06F2221/034
Abstract: An apparatus and method for intelligent power virus protection in a processor. For example, one embodiment of a processor comprises: first circuitry including an instruction fetch circuit to fetch instructions, each instruction comprising an instruction type and an associated width comprising a number of bits associated with source and/or destination operand values associated with the instruction; detection circuitry to detect one or more instructions of a particular type and/or width; evaluation circuitry to evaluate an impact of power virus protection (PVP) circuitry when executing the one or more instructions based on the detected instruction types and/or widths; and control circuitry, based on the evaluation, to configure the PVP circuitry in accordance with the evaluation performed by the evaluation circuitry.
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公开(公告)号：US11797456B2
公开(公告)日：2023-10-24
申请号：US17704909
申请日：2022-03-25
Applicant: Oracle International Corporation
Inventor： Benjamin John Fuller
IPC: G06F12/0891 , G06F1/32 , G06F12/0804 , G06F12/0831 , G06F13/16 , G06F1/30 , G06F12/0868
CPC classification number: G06F12/0891 , G06F1/32 , G06F12/0804 , G06F12/0833 , G06F13/1668 , G06F2212/60
Abstract: Techniques described herein provide a handshake mechanism and protocol for notifying an operating system whether system hardware supports persistent cache flushing. System firmware may determine whether the hardware is capable of supporting a full flush of processor caches and volatile memory buffers in the event of a power outage or asynchronous reset. If the hardware is capable, then persistent cache flushing may be selectively enabled and advertised to the operating system. Once persistent cache flushing is enabled, the operating system and applications may treat data committed to volatile processor caches as persistent. If disabled or not supported by system hardware, then the platform may not advertise support for persistent cache flushing to the operating system.
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公开(公告)号：US20230333622A1
公开(公告)日：2023-10-19
申请号：US18306699
申请日：2023-04-25
Applicant: Capital One Services, LLC
Inventor： Dennis GIBSON
CPC classification number: G06F1/30 , G06F1/32 , G04G13/026
Abstract: Techniques and apparatus for providing power monitoring processes are described. In one embodiment, for example, an apparatus may include at least one storage device and logic coupled to the at least one storage device. The logic may be configured to poll a power device comprising a plurality of power elements via an alarm status identifier operative to cause the power device to return an alarm status string comprising a plurality of alarm status bits, each of the plurality of alarm status bits indicating an active alarm state of one of the plurality of power elements, and determine each of the plurality of power elements in the active alarm state based on the alarm status string. Other embodiments are described.
