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公开(公告)号：US20240320184A1
公开(公告)日：2024-09-26
申请号：US18620284
申请日：2024-03-28
Applicant: Intel Corporation
Inventor： Altug Koker , Ben Ashbaugh , Scott Janus , Aravindh Anantaraman , Abhishek R. Appu , Niranjan Cooray , Varghese George , Arthur Hunter , Brent E. Insko , Elmoustapha Ould-Ahmed-Vall , Selvakumar Panneer , Vasanth Ranganathan , Joydeep Ray , Kamal Sinha , Lakshminarayanan Striramassarma , Prasoonkumar Surti , Saurabh Tangri
IPC: G06F15/78 , G06F7/544 , G06F7/575 , G06F7/58 , G06F9/30 , G06F9/38 , G06F9/50 , G06F12/02 , G06F12/06 , G06F12/0802 , G06F12/0804 , G06F12/0811 , G06F12/0862 , G06F12/0866 , G06F12/0871 , G06F12/0875 , G06F12/0882 , G06F12/0888 , G06F12/0891 , G06F12/0893 , G06F12/0895 , G06F12/0897 , G06F12/1009 , G06F12/128 , G06F15/80 , G06F17/16 , G06F17/18 , G06N3/08 , G06T1/20 , G06T1/60 , G06T15/06 , H03M7/46
CPC classification number: G06F15/7839 , G06F7/5443 , G06F7/575 , G06F7/588 , G06F9/3001 , G06F9/30014 , G06F9/30036 , G06F9/3004 , G06F9/30043 , G06F9/30047 , G06F9/30065 , G06F9/30079 , G06F9/3887 , G06F9/5011 , G06F9/5077 , G06F12/0215 , G06F12/0238 , G06F12/0246 , G06F12/0607 , G06F12/0802 , G06F12/0804 , G06F12/0811 , G06F12/0862 , G06F12/0866 , G06F12/0871 , G06F12/0875 , G06F12/0882 , G06F12/0888 , G06F12/0891 , G06F12/0893 , G06F12/0895 , G06F12/0897 , G06F12/1009 , G06F12/128 , G06F15/8046 , G06F17/16 , G06F17/18 , G06T1/20 , G06T1/60 , H03M7/46 , G06F9/3802 , G06F9/3818 , G06F9/3867 , G06F2212/1008 , G06F2212/1021 , G06F2212/1044 , G06F2212/302 , G06F2212/401 , G06F2212/455 , G06F2212/60 , G06N3/08 , G06T15/06
Abstract: Embodiments are generally directed to a multi-tile architecture for graphics operations. An embodiment of an apparatus includes a multi-tile architecture for graphics operations including a multi-tile graphics processor, the multi-tile processor includes one or more dies; multiple processor tiles installed on the one or more dies; and a structure to interconnect the processor tiles on the one or more dies, wherein the structure to enable communications between processor tiles the processor tiles.
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公开(公告)号：US12099461B2
公开(公告)日：2024-09-24
申请号：US17431034
申请日：2020-03-14
Applicant: Intel Corporation
Inventor： Abhishek R. Appu , Altug Koker , Aravindh Anantaraman , Elmoustapha Ould-Ahmed-Vall , Valentin Andrei , Nicolas Galoppo Von Borries , Varghese George , Mike Macpherson , Subramaniam Maiyuran , Joydeep Ray , Lakshminarayanan Striramassarma , Scott Janus , Brent Insko , Vasanth Ranganathan , Kamal Sinha , Arthur Hunter , Prasoonkumar Surti , David Puffer , James Valerio , Ankur N. Shah
IPC: G06F16/00 , G06F7/544 , G06F7/575 , G06F7/58 , G06F9/30 , G06F9/38 , G06F9/50 , G06F12/02 , G06F12/06 , G06F12/0802 , G06F12/0804 , G06F12/0811 , G06F12/0862 , G06F12/0866 , G06F12/0871 , G06F12/0875 , G06F12/0882 , G06F12/0888 , G06F12/0891 , G06F12/0893 , G06F12/0895 , G06F12/0897 , G06F12/1009 , G06F12/128 , G06F15/78 , G06F15/80 , G06F17/16 , G06F17/18 , G06T1/20 , G06T1/60 , H03M7/46 , G06N3/08 , G06T15/06
CPC classification number: G06F15/7839 , G06F7/5443 , G06F7/575 , G06F7/588 , G06F9/3001 , G06F9/30014 , G06F9/30036 , G06F9/3004 , G06F9/30043 , G06F9/30047 , G06F9/30065 , G06F9/30079 , G06F9/3887 , G06F9/5011 , G06F9/5077 , G06F12/0215 , G06F12/0238 , G06F12/0246 , G06F12/0607 , G06F12/0802 , G06F12/0804 , G06F12/0811 , G06F12/0862 , G06F12/0866 , G06F12/0871 , G06F12/0875 , G06F12/0882 , G06F12/0888 , G06F12/0891 , G06F12/0893 , G06F12/0895 , G06F12/0897 , G06F12/1009 , G06F12/128 , G06F15/8046 , G06F17/16 , G06F17/18 , G06T1/20 , G06T1/60 , H03M7/46 , G06F9/3802 , G06F9/3818 , G06F9/3867 , G06F2212/1008 , G06F2212/1021 , G06F2212/1044 , G06F2212/302 , G06F2212/401 , G06F2212/455 , G06F2212/60 , G06N3/08 , G06T15/06
Abstract: Methods and apparatus relating to techniques for multi-tile memory management. In an example, an apparatus comprises a cache memory, a high-bandwidth memory, a shader core communicatively coupled to the cache memory and comprising a processing element to decompress a first data element extracted from an in-memory database in the cache memory and having a first bit length to generate a second data element having a second bit length, greater than the first bit length, and an arithmetic logic unit (ALU) to compare the data element to a target value provided in a query of the in-memory database. Other embodiments are also disclosed and claimed.
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公开(公告)号：US20240104026A1
公开(公告)日：2024-03-28
申请号：US18535162
申请日：2023-12-11
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Naveen BHORIA , Timothy David ANDERSON , Pete HIPPLEHEUSER
IPC: G06F12/128 , G06F9/30 , G06F9/54 , G06F11/10 , G06F12/02 , G06F12/0802 , G06F12/0804 , G06F12/0806 , G06F12/0811 , G06F12/0815 , G06F12/0817 , G06F12/0853 , G06F12/0855 , G06F12/0864 , G06F12/0884 , G06F12/0888 , G06F12/0891 , G06F12/0895 , G06F12/0897 , G06F12/12 , G06F12/121 , G06F12/126 , G06F12/127 , G06F13/16 , G06F15/80 , G11C5/06 , G11C7/10 , G11C7/22 , G11C29/42 , G11C29/44
CPC classification number: G06F12/128 , G06F9/3001 , G06F9/30043 , G06F9/30047 , G06F9/546 , G06F11/1064 , G06F12/0215 , G06F12/0238 , G06F12/0292 , G06F12/0802 , G06F12/0804 , G06F12/0806 , G06F12/0811 , G06F12/0815 , G06F12/082 , G06F12/0853 , G06F12/0855 , G06F12/0864 , G06F12/0884 , G06F12/0888 , G06F12/0891 , G06F12/0895 , G06F12/0897 , G06F12/12 , G06F12/121 , G06F12/126 , G06F12/127 , G06F13/1605 , G06F13/1642 , G06F13/1673 , G06F13/1689 , G06F15/8069 , G11C5/066 , G11C7/10 , G11C7/1015 , G11C7/106 , G11C7/1075 , G11C7/1078 , G11C7/1087 , G11C7/222 , G11C29/42 , G11C29/44 , G06F2212/1016 , G06F2212/1021 , G06F2212/1024 , G06F2212/1041 , G06F2212/1044 , G06F2212/301 , G06F2212/454 , G06F2212/6032 , G06F2212/6042 , G06F2212/608 , G06F2212/62
Abstract: A caching system including a first sub-cache, and a second sub-cache, coupled in parallel with the first cache, for storing cache data evicted from the first sub-cache and write-memory commands that are not cached in the first sub-cache, and wherein the second sub-cache includes: color tag bits configured to store an indication that a corresponding cache line of the second sub-cache storing write miss data is associated with a color tag, and an eviction controller configured to evict cache lines of the second sub-cache storing write-miss data based on the color tag associated with the cache line.
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公开(公告)号：US20240078190A1
公开(公告)日：2024-03-07
申请号：US18497005
申请日：2023-10-30
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Naveen BHORIA , Timothy David ANDERSON , Pete HIPPLEHEUSER
IPC: G06F12/128 , G06F9/30 , G06F9/54 , G06F11/10 , G06F12/02 , G06F12/0802 , G06F12/0804 , G06F12/0806 , G06F12/0811 , G06F12/0815 , G06F12/0817 , G06F12/0853 , G06F12/0855 , G06F12/0864 , G06F12/0884 , G06F12/0888 , G06F12/0891 , G06F12/0895 , G06F12/0897 , G06F12/12 , G06F12/121 , G06F12/126 , G06F12/127 , G06F13/16 , G06F15/80 , G11C5/06 , G11C7/10 , G11C7/22 , G11C29/42 , G11C29/44
CPC classification number: G06F12/128 , G06F9/3001 , G06F9/30043 , G06F9/30047 , G06F9/546 , G06F11/1064 , G06F12/0215 , G06F12/0238 , G06F12/0292 , G06F12/0802 , G06F12/0804 , G06F12/0806 , G06F12/0811 , G06F12/0815 , G06F12/082 , G06F12/0853 , G06F12/0855 , G06F12/0864 , G06F12/0884 , G06F12/0888 , G06F12/0891 , G06F12/0895 , G06F12/0897 , G06F12/12 , G06F12/121 , G06F12/126 , G06F12/127 , G06F13/1605 , G06F13/1642 , G06F13/1673 , G06F13/1689 , G06F15/8069 , G11C5/066 , G11C7/10 , G11C7/1015 , G11C7/106 , G11C7/1075 , G11C7/1078 , G11C7/1087 , G11C7/222 , G11C29/42 , G11C29/44 , G06F2212/1016 , G06F2212/1021 , G06F2212/1024 , G06F2212/1041 , G06F2212/1044 , G06F2212/301 , G06F2212/454 , G06F2212/6032 , G06F2212/6042 , G06F2212/608 , G06F2212/62
Abstract: A caching system including a first sub-cache, a second sub-cache, coupled in parallel with the first sub-cache, for storing write-memory commands that are not cached in the first sub-cache, the second sub-cache including privilege bits configured to store an indication that a corresponding cache line of the second sub-cache is associated with a level of privilege, and wherein the second sub-cache is further configured to receive a first write memory command for a memory address associated with a first level of privilege, store, in the second sub-cache, first data associated with the first write memory command and the level of privilege associated with the cache line, receive a second write memory command for the cache line, the second write memory command associated with a second level of privilege, merge the first level of privilege with the second level of privilege, and output the merged privilege level with the cache line.
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公开(公告)号：US20240070069A1
公开(公告)日：2024-02-29
申请号：US18215474
申请日：2023-06-28
Applicant: Micron Technology, Inc.
Inventor： Brent Keeth , Owen Fay , Chan H. Yoo , Roy E. Greeff , Matthew B. Leslie
IPC: G06F12/06 , G06F12/02 , G11C11/4093 , G11C29/12 , H01L25/065 , H01L25/18
CPC classification number: G06F12/0653 , G06F12/0215 , G11C11/4093 , G11C29/12 , H01L25/0652 , H01L25/0657 , H01L25/18 , G06F2212/1016 , G11C2211/4062 , H01L2225/06506 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/0652 , H01L2225/06541 , H01L2225/06562 , H01L2225/06586
Abstract: Apparatus and methods are disclosed, including memory devices and systems. Example memory devices, systems and methods include a buffer interface to translate high speed data interactions on a host interface side into slower, wider data interactions on a DRAM interface side. The slower, and wider DRAM interface may be configured to substantially match the capacity of the narrower, higher speed host interface. In some examples, the buffer interface may be configured to provide multiple sub-channel interfaces each coupled to one or more regions within the memory structure and configured to facilitate data recovery in the event of a failure of some portion of the memory structure. Selected example memory devices, systems and methods include an individual DRAM die, or one or more stacks of DRAM dies coupled to a buffer die.
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公开(公告)号：US11899614B2
公开(公告)日：2024-02-13
申请号：US17849201
申请日：2022-06-24
Applicant: Intel Corporation
Inventor： Joydeep Ray , Altug Koker , Varghese George , Mike Macpherson , Aravindh Anantaraman , Abhishek R. Appu , Elmoustapha Ould-Ahmed-Vall , Nicolas Galoppo von Borries , Ben J. Ashbaugh
IPC: G06F15/78 , G06F9/30 , G06F9/38 , G06F17/18 , G06F12/0802 , G06F7/544 , G06F7/575 , G06F12/02 , G06F12/0866 , G06F12/0875 , G06F12/0895 , G06F12/128 , G06F12/06 , G06F12/1009 , G06T1/20 , G06T1/60 , H03M7/46 , G06F12/0811 , G06F15/80 , G06F17/16 , G06F7/58 , G06F12/0871 , G06F12/0862 , G06F12/0897 , G06F9/50 , G06F12/0804 , G06F12/0882 , G06F12/0891 , G06F12/0893 , G06F12/0888 , G06T15/06 , G06N3/08
CPC classification number: G06F15/7839 , G06F7/5443 , G06F7/575 , G06F7/588 , G06F9/3001 , G06F9/3004 , G06F9/30014 , G06F9/30036 , G06F9/30043 , G06F9/30047 , G06F9/30065 , G06F9/30079 , G06F9/3887 , G06F9/5011 , G06F9/5077 , G06F12/0215 , G06F12/0238 , G06F12/0246 , G06F12/0607 , G06F12/0802 , G06F12/0804 , G06F12/0811 , G06F12/0862 , G06F12/0866 , G06F12/0871 , G06F12/0875 , G06F12/0882 , G06F12/0888 , G06F12/0891 , G06F12/0893 , G06F12/0895 , G06F12/0897 , G06F12/1009 , G06F12/128 , G06F15/8046 , G06F17/16 , G06F17/18 , G06T1/20 , G06T1/60 , H03M7/46 , G06F9/3802 , G06F9/3818 , G06F9/3867 , G06F2212/1008 , G06F2212/1021 , G06F2212/1044 , G06F2212/302 , G06F2212/401 , G06F2212/455 , G06F2212/60 , G06N3/08 , G06T15/06
Abstract: Embodiments described herein provide techniques to facilitate instruction-based control of memory attributes. One embodiment provides a graphics processor comprising a processing resource, a memory device, a cache coupled with the processing resources and the memory, and circuitry to process a memory access message received from the processing resource. The memory access message enables access to data of the memory device. To process the memory access message, the circuitry is configured to determine one or more cache attributes that indicate whether the data should be read from or stored the cache. The cache attributes may be provided by the memory access message or stored in state data associated with the data to be accessed by the access message.
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公开(公告)号：US11886353B2
公开(公告)日：2024-01-30
申请号：US16882378
申请日：2020-05-22
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Naveen Bhoria , Timothy David Anderson , Pete Hippleheuser
IPC: G06F12/12 , G06F12/128 , G06F12/0888 , G06F12/0891 , G06F9/54 , G06F12/02 , G06F12/0811 , G06F12/0817 , G06F12/0804 , G06F9/30 , G11C7/10 , G11C29/42 , G11C29/44 , G06F11/10 , G06F12/0855 , G06F12/0806 , G06F12/0815 , G06F12/0853 , G06F13/16 , G06F12/121 , G06F12/0884 , G06F12/0897 , G06F12/0895 , G06F12/0864 , G11C7/22 , G11C5/06 , G06F15/80 , G06F12/0802 , G06F12/126 , G06F12/127
CPC classification number: G06F12/128 , G06F9/3001 , G06F9/30043 , G06F9/30047 , G06F9/546 , G06F11/1064 , G06F12/0215 , G06F12/0238 , G06F12/0292 , G06F12/0802 , G06F12/082 , G06F12/0804 , G06F12/0806 , G06F12/0811 , G06F12/0815 , G06F12/0853 , G06F12/0855 , G06F12/0864 , G06F12/0884 , G06F12/0888 , G06F12/0891 , G06F12/0895 , G06F12/0897 , G06F12/12 , G06F12/121 , G06F12/126 , G06F12/127 , G06F13/1605 , G06F13/1642 , G06F13/1673 , G06F13/1689 , G06F15/8069 , G11C5/066 , G11C7/10 , G11C7/106 , G11C7/1015 , G11C7/1075 , G11C7/1078 , G11C7/1087 , G11C7/222 , G11C29/42 , G11C29/44 , G06F2212/1016 , G06F2212/1021 , G06F2212/1024 , G06F2212/1041 , G06F2212/1044 , G06F2212/301 , G06F2212/454 , G06F2212/608 , G06F2212/6032 , G06F2212/6042 , G06F2212/62
Abstract: A caching system including a first sub-cache, and a second sub-cache, coupled in parallel with the first cache, for storing cache data evicted from the first sub-cache and write-memory commands that are not cached in the first sub-cache, and wherein the second sub-cache includes: color tag bits configured to store an indication that a corresponding cache line of the second sub-cache storing write miss data is associated with a color tag, and an eviction controller configured to evict cache lines of the second sub-cache storing write-miss data based on the color tag associated with the cache line.
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公开(公告)号：US11868272B2
公开(公告)日：2024-01-09
申请号：US17956960
申请日：2022-09-30
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Naveen Bhoria , Timothy David Anderson , Pete Michael Hippleheuser
IPC: G06F12/12 , G06F12/128 , G06F12/0888 , G06F12/0891 , G06F9/54 , G06F12/02 , G06F12/0811 , G06F12/0817 , G06F12/0804 , G06F9/30 , G11C7/10 , G11C29/42 , G11C29/44 , G06F11/10 , G06F12/0855 , G06F12/0806 , G06F12/0815 , G06F12/0853 , G06F13/16 , G06F12/121 , G06F12/0884 , G06F12/0897 , G06F12/0895 , G06F12/0864 , G11C7/22 , G11C5/06 , G06F15/80 , G06F12/0802 , G06F12/126 , G06F12/127
CPC classification number: G06F12/128 , G06F9/3001 , G06F9/30043 , G06F9/30047 , G06F9/546 , G06F11/1064 , G06F12/0215 , G06F12/0238 , G06F12/0292 , G06F12/0802 , G06F12/082 , G06F12/0804 , G06F12/0806 , G06F12/0811 , G06F12/0815 , G06F12/0853 , G06F12/0855 , G06F12/0864 , G06F12/0884 , G06F12/0888 , G06F12/0891 , G06F12/0895 , G06F12/0897 , G06F12/12 , G06F12/121 , G06F12/126 , G06F12/127 , G06F13/1605 , G06F13/1642 , G06F13/1673 , G06F13/1689 , G06F15/8069 , G11C5/066 , G11C7/10 , G11C7/106 , G11C7/1015 , G11C7/1075 , G11C7/1078 , G11C7/1087 , G11C7/222 , G11C29/42 , G11C29/44 , G06F2212/1016 , G06F2212/1021 , G06F2212/1024 , G06F2212/1041 , G06F2212/1044 , G06F2212/301 , G06F2212/454 , G06F2212/608 , G06F2212/6032 , G06F2212/6042 , G06F2212/62
Abstract: Methods, apparatus, systems and articles of manufacture are disclosed for allocation in a victim cache system. An example apparatus includes a first cache storage, a second cache storage, a cache controller coupled to the first cache storage and the second cache storage and operable to receive a memory operation that specifies an address, determine, based on the address, that the memory operation evicts a first set of data from the first cache storage, determine that the first set of data is unmodified relative to an extended memory, and cause the first set of data to be stored in the second cache storage.
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公开(公告)号：US11868253B2
公开(公告)日：2024-01-09
申请号：US17861627
申请日：2022-07-11
Applicant: Lodestar Licensing Group, LLC
Inventor： Brent Keeth , Owen Fay , Chan H. Yoo , Roy E. Greeff , Matthew B. Leslie
IPC: G11C11/00 , G06F12/06 , G11C29/12 , G11C11/4093 , H01L25/18 , H01L25/065 , G06F12/02
CPC classification number: G06F12/0653 , G06F12/0215 , G11C11/4093 , G11C29/12 , H01L25/0652 , H01L25/0657 , H01L25/18 , G06F2212/1016 , G11C2211/4062 , H01L2225/0651 , H01L2225/0652 , H01L2225/06506 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06562 , H01L2225/06586
Abstract: Memory devices, systems and methods include a buffer interface to translate high speed data interactions on a host interface side into slower, wider data interactions on a DRAM interface side. The slower, and wider DRAM interface may be configured to substantially match the capacity of the narrower, higher speed host interface. In some configurations, the buffer interface may be configured to provide multiple sub-channel interfaces each coupled to one or more regions within the memory structure and configured to facilitate data recovery in the event of a failure of some portion of the memory structure. Selected memory devices, systems and methods include an individual DRAM die, or one or more stacks of DRAM dies coupled to a buffer die.
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公开(公告)号：US20240004800A1
公开(公告)日：2024-01-04
申请号：US18469825
申请日：2023-09-19
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Naveen BHORIA , Timothy David ANDERSON , Pete HIPPLEHEUSER
IPC: G06F12/128 , G06F12/0888 , G06F12/0891 , G06F9/54 , G06F12/02 , G06F12/0811 , G06F12/0817 , G06F12/0804 , G06F9/30 , G11C7/10 , G11C29/42 , G11C29/44 , G06F11/10 , G06F12/0855 , G06F12/12 , G06F12/0806 , G06F12/0815 , G06F12/0853 , G06F13/16 , G06F12/121 , G06F12/0884 , G06F12/0897 , G06F12/0895 , G06F12/0864 , G11C7/22 , G11C5/06 , G06F15/80 , G06F12/0802 , G06F12/126 , G06F12/127
CPC classification number: G06F12/128 , G06F12/0888 , G06F12/0891 , G06F9/546 , G06F12/0215 , G06F12/0238 , G06F12/0811 , G06F12/082 , G06F12/0804 , G06F9/3001 , G06F9/30047 , G11C7/106 , G11C7/1087 , G11C29/42 , G11C29/44 , G06F11/1064 , G06F12/0855 , G06F12/12 , G06F12/0806 , G06F12/0815 , G06F12/0853 , G06F13/1605 , G06F12/121 , G06F12/0292 , G06F12/0884 , G06F12/0897 , G06F12/0895 , G06F12/0864 , G11C7/222 , G11C7/1075 , G11C7/1078 , G06F13/1642 , G06F13/1673 , G06F13/1689 , G11C5/066 , G11C7/10 , G11C7/1015 , G06F15/8069 , G06F12/0802 , G06F9/30043 , G06F12/126 , G06F12/127 , G06F2212/1021 , G06F2212/608 , G06F2212/6032 , G06F2212/1024 , G06F2212/62 , G06F2212/1016 , G06F2212/1041 , G06F2212/1044 , G06F2212/301 , G06F2212/454 , G06F2212/6042
Abstract: Techniques for caching data are provided that include receiving, by a caching system, a write memory command for a memory address, the write memory command associated with a first color tag, determining, by a first sub-cache of the caching system, that the memory address is not cached in the first sub-cache, determining, by second sub-cache of the caching system, that the memory address is not cached in the second sub-cache, storing first data associated with the first write memory command in a cache line of the second sub-cache, storing the first color tag in the second sub-cache, receiving a second write memory command for the cache line, the write memory command associated with a second color tag, merging the second color tag with the first color tag, storing the merged color tag, and evicting the cache line based on the merged color tag.
