公开(公告)号：US20190026228A1

公开(公告)日：2019-01-24

申请号：US15655711

申请日：2017-07-20

申请人： ALIBABA GROUP HOLDING LIMITED

发明人： Xiaowei JIANG

IPC分类号： G06F12/0888 ,  G06F12/084

CPC分类号： G06F12/0888 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/0846 ,  G06F12/1009 ,  G06F12/1027 ,  G06F2212/1021 ,  G06F2212/1024 ,  G06F2212/1028 ,  G06F2212/1041 ,  G06F2212/62

摘要： A multi-core CPU includes a Last-Level Cache (LLC) interconnected with a plurality of cores. The LLC may include a shared portion and a private portion. The shared portion may be shared by the plurality of cores. The private portion may be connected to a first core of the plurality of cores and may be exclusively assigned to the first core. The first core may be configured to initiate a data access request to access data stored in the LLC and initiate a data access request to access data stored in the LLC. The first core may route the data access request to the private portion based on the determination that the data access request is the TLS type of access request and route the data access request to the shared portion based on the determination that the data access request is not the TLS type of access request.

公开(公告)号：US20180348847A1

公开(公告)日：2018-12-06

申请号：US15607921

申请日：2017-05-30

申请人： Microsoft Technology Licensing, LLC

发明人： Patrick P. LAI ,  Robert Allen SHEARER

IPC分类号： G06F1/32

CPC分类号： G06F1/3275 ,  G06F1/3243 ,  G06F1/3287 ,  G06F12/0846 ,  G06F2212/1028

摘要： Processors may include cache circuitry that is a significant source of power consumption. A cache is going to be placed into a lower power mode. Based at least in part on this anticipated transition, the contents of the cache data lines are copied into persistent storage. While the cache is in the lower power mode, the tag circuitry is kept operational. When an access request is made to the cache, a relatively fast lookup of the tag in the tag array can be made. The location where the associated cache line is stored in the persistent storage may be determined from the tag data. Upon a tag hit, the system is able to find the contents of the requested cache line in the persistent storage without returning the storage array of the cache to a fully operational state.

公开(公告)号：US20180285261A1

公开(公告)日：2018-10-04

申请号：US15476816

申请日：2017-03-31

申请人： Intel Corporation

发明人： Ayan Mandal ,  Eran Shifer ,  Leon Polishuk

IPC分类号： G06F12/084 ,  G06F12/0846 ,  G06F12/0855 ,  G06F9/50 ,  G06F12/02 ,  G06F12/0888 ,  G06F12/1027 ,  G06F3/06

CPC分类号： G06F12/084 ,  G06F3/0653 ,  G06F9/5016 ,  G06F12/0223 ,  G06F12/0846 ,  G06F12/0855 ,  G06F12/0888 ,  G06F12/1027 ,  G06F2212/1028 ,  G06F2212/1044 ,  G06F2212/604 ,  G06F2212/6046

摘要： Technologies are provided in embodiments to dynamically fill a shared cache. At least some embodiments include determining that data requested in a first request for the data by a first processing device is not stored in a cache shared by the first processing device and a second processing device, where a dynamic fill policy is applicable to the first request. Embodiments further include determining to deallocate, based at least in part on a threshold, an entry in a buffer, the entry containing information corresponding to the first request for the data. Embodiments also include sending a second request for the data to a system memory, and sending the data from the system memory to the first processing device. In more specific embodiments, the data from the system memory is not written to the cache based, at least in part, on the determination to deallocate the entry.

公开(公告)号：US20180276143A1

公开(公告)日：2018-09-27

申请号：US15990816

申请日：2018-05-28

申请人： Nutanix, Inc.

发明人： Gary Jeffrey LITTLE ,  Huapeng YUAN ,  Karan GUPTA ,  Peter Scott WYCKOFF ,  Rickard Edward FAITH

IPC分类号： G06F12/128 ,  G06F12/0808

CPC分类号： G06F12/128 ,  G06F9/5083 ,  G06F12/0284 ,  G06F12/0811 ,  G06F12/0846 ,  G06F2212/1016 ,  G06F2212/152 ,  G06F2212/154 ,  G06F2212/502 ,  G06F2212/601 ,  G06F2212/70

摘要： Embodiments serve to balance overall performance of a finite-sized caching system having a first cache of a first cache size and a second cache of a second cache size. A tail portion and a head portion of each of the caches are defined wherein incoming data elements are initially stored in a respective head portion and wherein evicted data elements are evicted from a respective tail portion. Performance metrics are defined wherein a performance metric includes a predicted miss cost that would be incurred when replacing an evicted data elements. A quantitative function is defined to include cache performance metrics and a cache reallocation amount. The cache performance metrics are evaluated periodically to determine a then-current cache reallocation amount. The caches can be balanced by increasing the first cache size by the cache reallocation amount and decreasing the second cache size by the cache reallocation amount.

公开(公告)号：US20180165217A1

公开(公告)日：2018-06-14

申请号：US15378171

申请日：2016-12-14

申请人： Intel Corporation

发明人： Daniel Greenspan

IPC分类号： G06F12/0897

CPC分类号： G06F12/0897 ,  G06F12/08 ,  G06F12/0808 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0846 ,  G06F12/0855 ,  G06F12/0888 ,  G06F12/123 ,  G06F12/126 ,  G06F2212/1021 ,  G06F2212/1032 ,  G06F2212/1044 ,  G06F2212/608

摘要： In an embodiment, a processor includes at least one core and a first cache memory including a first plurality of sets having a first plurality of cache lines and associated metadata to store address information, recency information and a first indicator to indicate whether the cache line is associated with an oversubscribed set of a second cache memory. A first cache controller may be configured to base an eviction decision with regard to a first set of the first plurality of sets including a first cache line at least in part on the first indicator of the first cache line. Other embodiments are described and claimed.

公开(公告)号：US20180150398A1

公开(公告)日：2018-05-31

申请号：US15370113

申请日：2016-12-06

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shih-Lien Linus LU

IPC分类号： G06F12/0846

CPC分类号： G06F12/0864 ,  G06F11/1423 ,  G06F12/0846 ,  G06F2212/1016 ,  G06F2212/1032 ,  G06F2212/601 ,  G06F2212/608

摘要： An integrated circuit (IC) is provided. The IC includes a cache memory and an address decoder. The cache memory is divided into a plurality of groups. The address decoder provides a physical address according to an access address. When the access address corresponds to a specific group of the groups of the cache memory, the address decoder changes the access address to provide the physical address, and when the access address corresponds to one of the groups other than the specific group in the cache memory, the address decoder assigns the access address as the physical address.

公开(公告)号：US20180137054A1

公开(公告)日：2018-05-17

申请号：US15349203

申请日：2016-11-11

申请人： Microsoft Technology Licensing, LLC

发明人： Patrick P. Lai ,  Robert Allen Shearer

IPC分类号： G06F12/0864 ,  G06F12/0831 ,  G06F12/0853

CPC分类号： G06F12/0864 ,  G06F12/0831 ,  G06F12/0846 ,  G06F12/0853 ,  G06F2212/1016 ,  G06F2212/621 ,  Y02D10/13

摘要： A cache system is configurable to trade power consumption for cache access latency. When it is desired for a system with a cache to conserve dynamic power, the lookup of accesses (e.g., snoops) to cache tag ways is serialized to perform one (or less than all) tag way access per clock (or even slower). Thus, for an N-way set associative cache, instead of performing a lookup/comparison on the N tag ways in parallel, the lookups are performed one tag way at a time. This take N times more cycles thereby reducing the access/snoop bandwidth by a factor of N. However, the power consumption of the serialized access when compared to ‘all parallel’ accesses/snoops is reduced.

公开(公告)号：US09864703B2

公开(公告)日：2018-01-09

申请号：US14827958

申请日：2015-08-17

申请人： Teleputers, LLC

发明人： Ruby B. Lee ,  Zhenghong Wang

IPC分类号： G06F12/08 ,  G06F12/128 ,  G06F12/0802 ,  G06F12/0846 ,  G06F12/0891 ,  G06F12/0811 ,  G06F12/0864

CPC分类号： G06F12/128 ,  G06F12/0802 ,  G06F12/0811 ,  G06F12/0846 ,  G06F12/0864 ,  G06F12/0891 ,  G06F2212/1021 ,  Y02B70/30 ,  Y02D10/13

摘要： A cache memory having enhanced performance and security feature is provided. The cache memory includes a data array storing a plurality of data elements, a tag array storing a plurality of tags corresponding to the plurality of data elements, and an address decoder which permits dynamic memory-to-cache mapping to provide enhanced security of the data elements, as well as enhanced performance. The address decoder receives a context identifier and a plurality of index bits of an address passed to the cache memory, and determines whether a matching value in a line number register exists. The line number registers allow for dynamic memory-to-cache mapping, and their contents can be modified as desired. Methods for accessing and replacing data in a cache memory are also provided, wherein a plurality of index bits and a plurality of tag bits at the cache memory are received. The plurality of index bits are processed to determine whether a matching index exists in the cache memory and the plurality of tag bits are processed to determine whether a matching tag exists in the cache memory, and a data line is retrieved from the cache memory if both a matching tag and a matching index exist in the cache memory. A random line in the cache memory can be replaced with a data line from a main memory, or evicted without replacement, based on the combination of index and tag misses, security contexts and protection bits. User-defined and/or vendor-defined replacement procedures can be utilized to replace data lines in the cache memory.

公开(公告)号：US09798668B2

公开(公告)日：2017-10-24

申请号：US14891333

申请日：2014-12-14

申请人： VIA Alliance Semiconductor Co., Ltd.

发明人： Douglas R. Reed

IPC分类号： G06F12/08 ,  G06F12/0864 ,  G06F12/0846 ,  G06F12/123 ,  G06F12/128 ,  G06F12/0804

CPC分类号： G06F12/0864 ,  G06F12/0804 ,  G06F12/0846 ,  G06F12/123 ,  G06F12/128 ,  G06F2212/10 ,  G06F2212/1021 ,  G06F2212/601 ,  G06F2212/6032 ,  Y02D10/13

摘要： A cache memory stores 2^J-byte cache lines and includes an array of 2^N sets each holding tags each X bits, an input receives a Q-bit memory address, MA[(Q−1):0], having: a tag MA[(Q−1):(Q−X)] and an index MA[(Q−X−1):J]. Q is an integer at least (N+J+X−1). In a first mode: set selection logic selects one set using the index and LSB of the tag; comparison logic compares all but LSB of the tag with all but LSB of each tag in the selected set and indicates a hit if a match; otherwise allocation logic allocates into the selected set. In a second mode: the set selection logic selects two sets using the index; the comparison logic compares the tag with each tag in the selected two sets and indicates a hit if a match; and otherwise allocates into one set of the two selected sets.

公开(公告)号：US09792213B2

公开(公告)日：2017-10-17

申请号：US14847319

申请日：2015-09-08

申请人： International Business Machines Corporation

发明人： Deanna P. Berger ,  Michael F. Fee ,  Christine C. Jones ,  Arthur J. O'Neill ,  Diana L. Orf ,  Robert J. Sonnelitter, III

IPC分类号： G06F12/08 ,  G06F12/0855 ,  G06F12/0846 ,  G06F12/084

CPC分类号： G06F12/0857 ,  G06F12/084 ,  G06F12/0846 ,  G06F12/0855 ,  G06F2212/1024 ,  G06F2212/281

摘要： Various embodiments mitigate busy time in a hierarchical store-through memory cache structure including a cache directory associated with a memory cache. The cache directory is divided into a plurality of portions each associated with a portion of memory cache. A determination is made that a first subpipe of a shared cache pipeline comprises a non-store request. The shared pipeline is communicatively coupled to the plurality of portions of the cache directory. A store command is prevented from being placed in a second subpipe of the shared cache pipeline based on determining that a first subpipe of the shared cache pipeline comprises a non-store request. Simultaneous cache lookup operations are supported between the plurality of portions of the cache directory and cache write operations. Two or more store commands simultaneously processed in a shared cache pipeline communicatively coupled to the plurality of portions of the cache directory.